Patents Assigned to Condor Computing Corporation
  • Apparatus and Method for Selecting Dynamic Latency for Level 2 Cache
    Publication number: 20230409489
    Abstract: A processor includes a time counter and issuing instruction and executing instruction at a future time which is based on the time counter. The execution times are based on fixed latency times of instructions with exception of the load instruction which is based on the data cache hit latency time. A data cache miss causes the load instruction to fetch data from the level 2 cache wherein a time tracker unit adjusts the level 2 cache latency time based on a counter.
    Type: Application
    Filed: August 25, 2023
    Publication date: December 21, 2023
    Applicant: Condor Computing Corporation
    Inventors: Thang Tran, Shashank Nemawarkar, Raul Garibay