Patents Assigned to Condor Computing Corporation
  • Apparatus and method for selecting dynamic latency for level 2 cache
    Patent number: 12572480
    Abstract: A processor includes a time counter and issuing instruction and executing instruction at a future time which is based on the time counter. The execution times are based on fixed latency times of instructions with exception of the load instruction which is based on the data cache hit latency time. A data cache miss causes the load instruction to fetch data from the level 2 cache wherein a time tracker unit adjusts the level 2 cache latency time based on a counter.
    Type: Grant
    Filed: August 25, 2023
    Date of Patent: March 10, 2026
    Assignee: Condor Computing Corporation
    Inventors: Thang Tran, Shashank Nemawarkar, Raul Garibay
  • Apparatus and method for improving instruction fusion, fracture, and binary translation
    Patent number: 12561141
    Abstract: An electronic, digital data processor is adapted dynamically to develop for selected instructions received for execution in a pipelined execution unit a predetermined transform of the selected instructions. Depending on predetermined static or dynamic conditions that may exist in the pipelined execution unit, execution of the transform may be allowed or suppressed. The transform may be a fusion, a fracture or a binary transformation. A method is also disclosed for implementing this selective suppression of developed transforms.
    Type: Grant
    Filed: April 15, 2024
    Date of Patent: February 24, 2026
    Assignee: Condor Computing Corporation
    Inventor: Jeffrey L Nye
  • Apparatus and Method for Improving Instruction Fusion, Fracture, and Binary Translation
    Publication number: 20250321743
    Abstract: An electronic, digital data processor is adapted dynamically to develop for selected instructions received for execution in a pipelined execution unit a predetermined transform of the selected instructions. Depending on predetermined static or dynamic conditions that may exist in the pipelined execution unit, execution of the transform may be allowed or suppressed. The transform may be a fusion, a fracture or a binary transformation. A method is also disclosed for implementing this selective suppression of developed transforms.
    Type: Application
    Filed: April 15, 2024
    Publication date: October 16, 2025
    Applicant: Condor Computing Corporation
    Inventor: Jeffrey L. Nye
  • Apparatus and Method for Implementing a Loop Prediction of Multiple Basic Blocks
    Publication number: 20240394064
    Abstract: A processor includes a branch execution unit to detect a dual basic-block loop type where a second basic block jumps to the start address of a first basic block. The dual basic-block loop includes a predicted loop count to write to an entry of a branch target buffer (BTB). Two basic-blocks loop of the loop prediction from BTB forms a loop buffer in an instruction queues of the processor to seamlessly sending loop instructions from plurality of iterations to the next pipeline stage.
    Type: Application
    Filed: August 6, 2024
    Publication date: November 28, 2024
    Applicant: Condor Computing Corporation
    Inventor: Thang Tran
  • Apparatus and Method for Selecting Dynamic Latency for Level 2 Cache
    Publication number: 20230409489
    Abstract: A processor includes a time counter and issuing instruction and executing instruction at a future time which is based on the time counter. The execution times are based on fixed latency times of instructions with exception of the load instruction which is based on the data cache hit latency time. A data cache miss causes the load instruction to fetch data from the level 2 cache wherein a time tracker unit adjusts the level 2 cache latency time based on a counter.
    Type: Application
    Filed: August 25, 2023
    Publication date: December 21, 2023
    Applicant: Condor Computing Corporation
    Inventors: Thang Tran, Shashank Nemawarkar, Raul Garibay