Abstract: A data processing apparatus having a pipeline computer architecture with an input pipeline latch is disclosed. The data processing apparatus includes an ALU that executes a plurality of processing instructions. At least some of the instructions have an immediate data format including a field for intermediate data and a field for specifying a destination for an output. The ALU uses two operands for performing at least some of the instructions having the immediate data format. The ALU conditionally accepts either the contents of the input pipeline latch or the ALU output of the previous instruction as a second operand to an immediate instruction depending on the destination specified in the destination field of the previous instruction.

Abstract: Methods and apparatus are disclosed for shaping and controlling the spectrum of transmitted samples with a set of predetermined frequency characteristics and a predetermined set of allowable transmitted signal levels are disclosed. In particular, methods of minimizing the energy of the signal at unwanted frequencies are described. For each of the transmitted samples, the system computes a running measure of unwanted components. It then computes, for each block (or "data frame") of the transmitted samples, an objective function, for example, a running filter sum based upon a biquad filter function. It then selects, for each block or spectral shaping frame of transmitted samples, a sign combination from a sign-combination subset such that the objective function is optimized.

Abstract: A non-linear power amplifier for amplifying a constant envelope phase modulation component of a modulation signal and combining an amplitude envelope component of the modulation signal into the amplified constant envelope phase modulation component and method for performing the same. The power amplifier receives a constant envelope phase modulation signal and transmits the signal through a pair of amplifier stages which are impedance matched together. The first amplifier stage has a fixed gain which drives an impedance load and, in turn, the second amplifier stage. A variable resistance device is connected between a base of an amplifying transistor in the second amplifier stage and electrical ground for variably controlling the gain of the second amplifier stage by variably controlling the base-to-ground resistance of the amplifying transistor in the second amplifier stage.

Abstract: A pulse code modulation (PCM) modem system employs a relatively white training signal to optimize the adaptive filter coefficients in the receiver equalizers. During the training mode, any line coding or equivalent spectral shaping is disabled to provide a training signal sequence having a substantially even spectral content. The presence of DC within the training signal reduces the likelihood that the error function of the equalizers will settle at a local minimum. Following the training interval, the encoder enables the line coder to condition the digital input sequences, introduce DC nulls, and reduce the detrimental effects of baseline wander.

Abstract: An apparatus and corresponding method are provided for regulating the voltage potential of a lithium ion battery based upon an operating range having an upper threshold (e.g., on the order of 4.2 v) and a lower threshold (e.g., on the order of 2.5 v) and for providing a reduction in dissipated power when the lithium ion battery is charging and when a load is drawing upon the lithium ion battery. The apparatus includes a p-minus substrate and a first p-channel enhancement Field Effect Transistor (FET) integrally formed on the p-minus substrate. The first p-channel enhancement FET is configured to limit charging of the lithium ion battery when the voltage potential of the lithium ion battery is greater than the upper threshold.

Abstract: A multi-chip module made by using a direct attach method for manufacturing a multi-chip module by manufacturing a plurality of chips using a direct attach method and encapsulating the multi-chip models. The direct-attach method of manufacturing includes providing a special-design printed circuit board, manufacturing a lead frame with special design features including a central cavity for accommodating the specially designed printed circuit board and chips, assembling the lead frame and the printed circuit board using a conductive epoxy and curing the lead frame and printed circuit board assembly. The special-design printed circuit board includes a plurality of locating holes used for aligning the lead frame with the printed circuit board, a plurality of peripheral holes adapted to receive a corresponding lead frame finger, non-pointed corners, a silver or gold final plurality and a dry film.

Abstract: The n-bit A/D converter of the present invention includes a resistor network, n comparators, and (2.sup.n -1-n) multiplexers. The resistor network generates a plurality of reference voltages characterized by uniform voltage increments between two fixed voltages. The n comparators are coupled to the resistor network. Each comparator receives a reference voltage and an analog input signal. Based on these inputs, an ith comparator generates an ith bit output in the n-bit digital signal where i ranges from 1 to n with the first bit being the most-significant-bit and the nth bit being the least-significant-bit. The (2.sup.n -1-n) multiplexers are coupled between the resistor network and the ith comparator. In response to the output of comparators (except for the first comparator) associated with the more significant bits, the (2.sup.i-1 -1) multiplexers select a reference voltage and transmit it to the ith comparator.

Abstract: A cordless telephone system connectable to the public switched telephone network having a base station and one or more handsets communicating with the base station by an RF link using a time division duplex direct sequence spread spectrum quadrature modulation technique, having a gain imbalance compensation system for balancing the gain between the I and Q channels. Gain imbalance estimation is performed as part of a calibration cycle when the handset is in the cradle of the base station. The controller of the unit causes another unit to send a data signal with a frequency error. The baseband receiver performs the operation .vertline.I.vertline.-.vertline.Q.vertline., which is an indication of gain error. The results are stored in an accumulator over a set period of time. The controller reads the accumulator and uses an iterative process, increasing or decreasing the gain link compensation until no gain imbalance error is obtained.

Abstract: A circuit and method for Ethernet combination chaining of auto-negotiation sessions for multiple physical layer capability. The present invention provides control circuitry for arbitrating between different physical layer circuit types that heretofore were allowed autonomous auto-negotiation processes because only one type of physical layer circuitry was applied at each end of a communication line. The present invention operates effectively within a hub of a local area network (LAN) communication system where multiple communication standards can be employed within circuitry that communicate at different ends of a communication line, e.g., twisted pair wire. In the environment of the invention, different types of physical layer circuits are integrated within communication devices. The invention provides a mechanism whereby, at each end of the communication line, a first physical layer circuit (e.g., the master) of a first type is allowed to auto-negotiate under the IEEE 802.

Abstract: A GPS receiver engine is provided having a software interface between the GPS and local applications. The GPS manufacturer provides to the local manufacturer a GPS Chip Set that includes hardware components and software components. The hardware components can include an RF circuit and a processor. The software components can include an object code library and interface files that are used to interface with the local application software. The local manufacturer customizes its local application software to run with the software interface provided by the software components of the GPS Chip Set, stores the GPS software and the local application software into a memory system, and incorporates the RF circuit, processor and memory system into its GPS end product.

Abstract: The concept of integer ratio sample rate conversion is extended to fractional values, where the exact ratio is expressed as ?M+N/D!/L with L being a constant. This methodology allows sample rate conversion for all synchronous rates, where all rates are derived from the same crystal oscillator. For the implementation, the value of N/D is accumulated and depending on the overflow condition, either M or M+1 is selected as sample rate ratio for the conversion of each sample.

Abstract: A methodology for a modem control channel is disclosed. The channel allows faster seamless rate change and precoder tap exchange than the baseline procedure for seamless rate change, allowing for more robust transmission of control information. It can also be use to convey side-information in the case of multiple data applications, serving the purpose of mode switching. Thus, with a single control channel both the needs for seamless rate change and transmitting control information for multiple data applications can be met.

Abstract: A novel system by which the utilization of a central processing unit (CPU) in performing filtering operations can be reduced by shortening the filter's length thus degrading the performance of the system down to a predetermined level or threshold. The present invention is applicable to such systems that incorporate filters whereby shortening their length decreases the performance of the system and to such systems where a reliable quality criteria exists that can be measured during run time. A method iteratively minimizes the filter's length so that the quality criteria does not fall below a predetemined threshold level. In addition, a signal to noise ratio (SN) criteria is suggested for estimating the quality of the reception of communication signals. An implementation is suggested for the method in the particular case of an echo cancellation adaptive filter. In addition, a method for determining an immediate approximation of the echo canceler filter's length as opposed to finding it iteratively.