Abstract: An apparatus and method for issue grouping of instructions in a VLIW processor is disclosed. There can be one, two, or three issue groups (but no greater than three issue groups) in each VLIW packet. In one embodiment, a template in the VLIW packet comprises two issue group end markers where each issue group end marker comprises three bits. The three bits in the first issue group end marker identifies the instruction which is the last instruction in the first issue group. Likewise, the three bits in the second issue group end marker identifies the instruction which is the last instruction in the second issue group. Any instructions in the VLIW packet falling outside the two expressly defined first and second issue groups are placed in a third issue group. As such, three issue groups can be identified by use of the two issue group end markers. In one embodiment, the template of the VLIW packet includes a chaining bit.