Abstract: A shared memory stores packets for a packet processor. The shared memory is arranged into banks that are word-interleaved. All banks may be accessed in parallel during each time-slot by different requesters. A staggered round-robin arbiter connects requesters to banks in a parallel fashion. Requestor inputs to the arbiter are staggered to allow access to different banks in a sequential order over successive time-slots. Multi-processor tribes have many processors that generate random requests to the shared memory. A slot scheduler arranges these random requests into a stream of sequential requests that are synchronized to the staggered round-robin arbiter. A packet interface requestor stores incoming packets from an external network into the shared memory. The packet's offset within pages of the shared memory is determined by the first available bank that the packet can be written to, eliminating delays in storing incoming packets and spreading storage of frequently-accessed fields.

Abstract: A resource-lock monitor detects when processors in a multi-processor system are stuck waiting for access to a shared resource. A lock-monitor register has a lock bit and a sticky-lock bit for each processor being monitored. The lock and the sticky-lock bits are both set when the processor executes a lock instruction that also sends a lock-request to a resource arbiter. The lock bit is cleared when the resource arbiter grants access to the processor, but the sticky-lock bit remains set until sticky-lock bits are cleared by monitoring software at the end of a monitoring period. At the end of each monitoring period, monitoring software reads the lock and sticky-lock bits and finds a locked processor when a processor's lock bit is still set, but its sticky-lock bit is cleared. When the locked processor remains locked at the end of another monitoring period, an error handler resets the locked processor.

Abstract: A processing engine to accomplish a multiplicity of tasks has a multiplicity of processing tribes, each tribe comprising a multiplicity of context register sets and a multiplicity of processing resources for concurrent processing of a multiplicity of threads to accomplish the tasks, a memory structure having a multiplicity of memory blocks, each block storing data for processing threads, and an interconnect structure and control system enabling tribe-to-tribe migration of contexts to move threads from tribe-to-tribe. The processing engine is characterized in that individual ones of the tribes have preferential access to individual ones of the multiplicity of memory blocks.