Abstract: An input voltage controlled oscillator circuit for a digital video time base corrector used to process television signals to remove time base errors introduced during signal recording, reproducing, or transmission. In the time base corrector, incoming video signals are converted from analog-to-digital form, temporarily stored in a memory unit at a clocking rate which varies in a manner generally proportional to the time base errors, and the stored signals are fetched at a standard clocking rate.The input voltage controlled oscillator circuit generates the clock signals for performing the analog-to-digital conversion and for storing the digital signals in the memory unit. The frequency of the clock signals varies in accordance with the time base errors in the composite sync and burst portions of the incoming video signals.

Abstract: A method and apparatus for synchronizing unrelated video type signals from two different sources without employing feedback loops between the two sources.Incoming video signals are converted from analog to digital form and are clocked into a shift register unit by input clock signals phase and frequency locked to the instantaneous horizontal frequency and the color burst frequency portions of the incoming signal. The digitized video signals progressing along the shift register are stored at the input clock signal rate in a random access (RAM) having a sufficient capacity to provide continuous output video signals during each field. The signals are clocked out from the RAM by output clock signals derived from the sync and color burst portions of a local signal comprising either composite video or composite color burst, which are synchronized with the local sync generator.

Abstract: A sequence control unit for a digital video time base corrector used to process television signals to remove time base errors introduced during signal recording, reproducing, or transmission. In the time base corrector, incoming video signals are converted from analog to digital form, temporarily stored in a memory unit at a clocking rate which varies in a manner generally proportional to the time base errors, and the stored signals are fetched at a standard clocking rate. The sequence control unit controls contemporaneous storing and fetching from different portions of the memory unit and includes circuitry for preventing application of both store and fetch signals to the same memory unit portion when the accumulated time base error would cause such an overlap condition.