Abstract: A thermoelectric generator of compact size, having a simple structure configured for increasing the conversion efficiency of thermal energy into electric energy, so as it is possible to transform into electric current also as amount of heat per unit surface greater than thin film prior art devices, has a base silicon wafer and a cover silicon wafer, wherein the cover silicon wafer is facing said base silicon wafer in such a way that the respective top contacts are in contact and the space between the cover silicon wafer and the base silicon wafer is a space in which vacuum is made or a gas is present, in particular air.

Abstract: An integrated thermoelectric generator of out-of-plane heat flux configuration can be fabricated with a process fully compatible with standard front-end CMOS or BiCMOS technologies, if portions of the planar electrically non conductive cover layer suspended over the valleys have sufficiently large through holes to let isotropic etching solutions or etching plasma pass therethrough, across the thickness of the non conductive cover layer, so as to realize void spaces. The generator has a top capping layer deposited onto a free surface, oriented in an opposite direction in respect to the void spaces, of the planar electrically non conductive cover layer so as to occlude the through holes of the non conductive cover layer. A method of fabricating an integrated thermoelectric generator of out-of-plane heat flux configuration is also disclosed.

Abstract: An enhanced electrical yield is achieved with an integrated thermoelectric generator (iTEG) of out-of-plane heat flux configuration on a substrate wafer having hill-top junction metal contacts and valley-bottom junction metal contacts joining juxtaposed ends of segments, alternately p-doped and n-doped, of defined thin film lines of segments of a polycrystalline semiconductor, extending over inclined opposite flanks of hills of a material of lower thermal conductivity than the thermal conductivity of the thermoelectrically active polycrystalline semiconductor, by keeping void the valleys spaces (V) among the hills and delimited at the top by a planar electrically non conductive cover with metal bond pads defined over the coupling surface, adapted to bond with respective hill-top junction metal contacts. The junction metal contacts have a cross sectional profile of low aspect ratio, with two arms or wings overlapping the juxtaposed end portions of the segments.

Abstract: Disclosed are two geometrically identical integrated Z-device structures, integrated in two distinct silicon dices, joined together in a face-to-face configuration, such that a p-doped thin film leg of one structure faces toward a n-doped thin film leg of the other structure and vice versa. Upon joining the Z-device structures together, the hill-top metal contacts of one integrated structure are bonded in electrical and thermal continuity with correspondent hill-top metal contacts of the other integrated structure, forming a substantially bivalve TEG of increased power yield for the same footprint area and having an enhanced conversion efficiency. Thermo-electrically generated current may be gathered from one or several end pad pairs, the pads of which are connected to respective valley bottom contacts, on one and on the other of the two dices of the bivalve device, at the ends of conductive lines of micro cells respectively belonging to one and to the other of the two coupled dices.

Abstract: Dices of integrated Z-device structures on a substrate wafer of a 3D integrated thermo-electric generator (iTEG) may be stacked in a tri-dimensional heterogeneous integration mode, without or with interposer wafer dices, in coherent thermal coupling among them. Through silicon vias (TSVs) holes through the thickness of the semiconductor crystal of substrate of the dices of integrated Z-device structures in geometrical projection correspondence with valley bottom metal junction contacts, and through silicon vias (TSVs) holes through the thickness of the semiconductor crystal of interposer dices, in geometrical projection correspondence with the hill-top metal junction contacts of the coupled Z-device structures, have a copper or other good heat conductor filler, form low thermal resistance heat conduction paths through the stacked Z-device structures. Thermoelectrically generated current is gathered from every integrated Z-device of a multi-tier iTEG operating in an out-of-plane heat flux configuration.

Abstract: A novel and effective structure of a stackable element (A1, A2) or more generally adapted to be associated modularly to other similar elements to form a septum of relatively large dimensions for a Seebeck/Peltier thermoelectric conversion device, may be fabricated with common planar processing techniques. The structure basically consists of a stack (A1, A2) of alternated layers of a first dielectric material (2), adapted to be deposited in films of thickness lesser than or equal to about 50 nm, of low heat conductivity and which is etchable by a solution of a specific chemical compound, and of a second dielectric material (3) of low heat conductivity that is not etched by the solution.

Abstract: The invention relates to Seebeck/Peltier bidirectional thermoelectric conversion devices and in particular to devices employing nanowires of conductive or semiconductive material defined on a substrate by common planar technologies.

Abstract: Significant phonon migration restraint is achieved within a relatively homogeneous polycrystalline doped semiconductor bulk by purposely creating in the crystal lattice of the semiconductor hydrocarbon bonds with the semiconductor, typically Si or Ge, constituting effective organic group substituents of semiconductor atoms in the crystalline domains. An important enhancement of the factor of merit Z of such a modified electrically conductive doped semiconductor is obtained without resorting to nanometric cross sectional dimensions in order to rely on surface scattering eventually enhanced by making the surface highly irregular and/or creating nanocavities within the bulk of the conductive material. A determinant scattering of phonons migrating under the influence and in the direction of a temperature gradient in the homogeneous semiconductor takes place at the organic groups substituents in the crystalline doped semiconductor bulk.

Abstract: The disclosure relates to Seebeck/Peltier effect thermoelectric conversion devices and in particular devices made of stack of dielectric layers alternated to treated semiconducting layers even of large size, not requiring lithographic patterning in a nano-micrometric scale.

Abstract: Significant phonon migration restraint is achieved within a relatively homogeneous polycrystalline doped semiconductor bulk by purposely creating in the crystal lattice of the semiconductor hydrocarbon bonds with the semiconductor, typically Si or Ge, constituting effective organic group substituents of semiconductor atoms in the crystalline domains. An important enhancement of the factor of merit Z of such a modified electrically conductive doped semiconductor is obtained without resorting to nanometric cross sectional dimensions in order to rely on surface scattering eventually enhanced by making the surface highly irregular and/or creating nanocavities within the bulk of the conductive material. A determinant scattering of phonons migrating under the influence and in the direction of a temperature gradient in the homogeneous semiconductor takes place at the organic groups substituents in the crystalline doped semiconductor bulk.

Abstract: A novel and effective structure of a stackable element (A1,A2) or more generally adapted to be associated modularly to other similar elements to form a septum of relatively large dimensions for a Seebeck/Peltier thermoelectric conversion device, may be fabricated with common planar processing techniques. The structure basically consists of a stack (A1, A2) of alternated layers of a first dielectric material (2), adapted to be deposited in films of thickness lesser than or equal to about 50 nm, of low heat conductivity and which is etchable by a solution of a specific chemical compound, and of a second dielectric material (3) of low heat conductivity that is not etched by the solution.

Abstract: A multilayered stack useful for constituting a Seebeck-Peltier effect electrically conductive septum with opposite hot-side and cold-side metallizations for connection to an electrical circuit, comprises a stacked succession of layers (Ci) of electrically conductive material alternated to dielectric oxide layers (Di) in form of a continuous film or of densely dispersed nano and sub-nano particles or clusters of particles of oxide; at least the electrically conductive layers having mean thickness ranging from 5 to 100 nm and surface irregularities at the interfaces with the dielectric oxide layers of mean peak-to-valley amplitude and mean periodicity comprised between 5 to 20 nm. Various processes adapted to build a multilayered stack of these characteristics are described.