Abstract: Static current consumption in a low-side output drive stage is eliminated by employing a switch in series with a current generator that is employed for controlling the discharge process of the driving node (gate) of the output power transistor and by controlling the switch with the voltage that is present on the driving node of the out put power transistor.

Abstract: A process for manufacturing high-density MOS-technology power devices includes the steps of: forming a conductive insulated gate layer on a surface of a lightly doped semiconductor material layer of a first conductivity type; forming an insulating material layer over the insulated gate layer; selectively removing the insulating material layer and the underlying insulated gate layer to form a plurality of elongated windows having two elongated edges and two short edges, delimiting respective uncovered surface stripes of the semiconductor material layer; implanting a high dose of a first dopant of the first conductivity type along two directions which lie in a plane transversal to said elongated windows and orthogonal to the semiconductor material layer surface, and which are substantially symmetrically tilted at a first prescribed angle with respect to a direction orthogonal to the semiconductor material layer surface, the first angle depending on the overall thickness of the insulated gate layer and of the in

Abstract: A package for semiconductor devices is encapsulated in an insulating resin. Multiple conductive leads project from one side of the package. Alternating leads are provided with an insulating coating which projects along a portion of their length. Leads which are not insulated are bent so as to displace them from the plane of the coated leads and space them further away from the coated leads. The bent leads are displaced a sufficient distance to provide a separation in air consistent with spacing standards for high voltage devices.

Abstract: Switching and propagation delays in generating a PWM control signal by a circuit that generally includes an error amplifier, a sawtooth oscillator and a comparator for comparing the error signal with the sawtooth signal, is compensated by generating a second sawtooth signal synchronous with the master sawtooth signal but having a reduced discharge time and by applying the second synchronous sawtooth signal to the respective input of the PWM comparator.

Abstract: A high-frequency bipolar transistor structure includes a base region of a first conductivity type formed in a silicon layer of a second conductivity type, the base region comprising an intrinsic base region surrounded by an extrinsic base region, an emitter region of the second conductivity type formed inside the intrinsic base region, the extrinsic base region and the emitter region being contacted by a first polysilicon layer and a second polysilicon layer respectively. The first and the second polysilicon layers are respectively contacted by a base metal electrode and an emitter metal electrode. Between the extrinsic base region and the first polysilicon layer, a silicide layer is provided to reduce the extrinsic base resistance of the bipolar transistor.

Abstract: The present invention relates to an electronic device integrated monolithlly on a semiconductor material comprising a substrate having a first conductivity type in which are formed first and second diffusion regions of a second conductivity type. The substrate and the first and second diffusion regions defining a base region, a collector region and an emitter region of a parasitic transistor. The second diffusion region includes a third diffusion region having conductivity of the first type to provide in the second diffusion region a resistive path placed in series with the emitter region of the parasitic transistor while backfeeding it negatively and taking it to saturation with a resulting reduction of its current gain and limitation of the maximum current due thereto.

Abstract: A monolithically integrated, transistor bridge circuit of a type suiting power applications, comprises at least one pair of IGBT transistors (M1,M2) together with vertically-conducting bipolar junction transistors transistors (T1,T2). These IGBT transistors are laterally conducting, having drain terminals (9,19) formed on the surface of the integrated circuit (1), and through such terminals, they are connected to another pair of transistors (T1,T2) of the bipolar type.

Abstract: The process provides first for the accomplishment of low-doping body regions at the sides and under a gate region and then the accomplishment of high-doping body regions inside said low-doping body regions and self-aligned with said gate region. There is thus obtained an MOS power transistor with vertical current flow which has high-doping body regions self-aligned with said gate region and with a reduced junction depth.

Abstract: A smart power integrated circuit, in which the power stage includes a vertical-current-flow NMOS power transistor having many paralleled cells. A deeper P-type diffusion surrounds the P-type body region of the cells at the edge of the power stage. The junction between this deep P-type diffusion and the laterally adjacent N-type material has a lower curvature than the junction which would be formed by the P-type body region alone. This increases the transistor's breakdown voltage without degrading the transistor's on-state resistance R.sub.on.