Abstract: A fuzzy device for image noise reduction, includes an interface adapted to retrieve the gray level of a pixel to be processed of an image and of neighbouring pixels; a difference circuit connected to the interface and adapted to generate a difference of the gray levels between said neighbouring pixels and said pixels to be processed; a fuzzy flat area smoothing circuit connected to the difference circuit and adapted to perform a low-pass smoothing of an almost homogeneous region defined by said pixel and by said neighbouring pixels; an edge preserving smoothing circuit connected to the difference circuit and adapted to perform low-pass filtering on a high-frequency information region defined by the pixel and by the neighbouring pixels; a region voter circuit connected to the interface and adapted to give a measure for considering whether the region defined by the pixel and the neighbouring pixels is almost homogeneous; and a soft switching circuit connected to the outputs of the smoothing circuit and adapted

Abstract: A manufacturing process for an integrated circuit which includes at least one vertical-current-flow MOS transistor. The patterned photoresist which screens the body implant is also used to mask the etching of a nitride layer over a pad oxide. After the photoresist is cleared, the nitride pattern is transferred into the oxide, and the resulting oxide/nitride stack is used to mask the source implant. The nitride/oxide stack is then removed, the gate oxide is grown, and the gate layer is then deposited.

Abstract: A bipolar control transistor, forming part of an integrated current-limiter device comprises inside an epitaxial layer superimposed over a semiconductor substrate of a first type of conductivity, a base region of a second type of conductivity accessible from a base contact and regions of collector and emitter of the first type of conductivity contained in the base region and accessible from respective collector and emitter contacts. The base region comprises at least one highly-doped deep-body region which contains almost completely said emitter region, a lightly-doped body region which contains the collector region and an intermediate-doped region which co-operates with the first deep-body region to completely contain the emitter region and a surface area of the base region that is included between the regions of collector and emitter.

Abstract: A PIC structure includes a lightly doped semiconductor layer of the first conductivity type superimposed over a heavily doped semiconductor substrate of a second conductivity type, wherein a Vertical IGBT and a driving and control circuit including at least first conductivity type-channel MOSFETs are integrated. The MOSFETs are provided inside well regions of the second conductivity type which are included in at least one lightly doped region of the first conductivity type completely surrounded and isolated from the lightly doped layer of the first conductivity type by means of a respective isolated region of a second conductivity type.

Abstract: An integrated edge structure for a high voltage semiconductor device comprising a PN junction represented by a diffused region of a first conductivity type extending from a semiconductor device top surface is described. The edge structure comprises a first, lightly doped ring of the first conductivity type obtained in a first, lightly doped epitaxial layer of a second conductivity type and surrounding said diffused region, and a second, lightly doped ring of the first conductivity type, comprising at least one portion superimposed on and merged with said first ring, obtained in a second, lightly doped epitaxial layer of the second conductivity type grown over the first epitaxial layer.

Abstract: A circuit for connecting a first circuit node to either a second or a third circuit node relative to the voltage potential on the third circuit node includes two bipolar transistors connected in series. The collectors of both transistors are connected to the first circuit node. The emitter of the first transistor is connected to the second circuit node and the emitter of the second transistor is connected to the third circuit node. Means are provided for maintaining the base of the second transistor at a constant, preset bias voltage.