Patents Assigned to ConTech Inc.
  • Patent number: 7217138
    Abstract: An interconnect assembly includes a number of interconnect stages combined in a carrier structure. Each interconnect stage includes at least two contact sets having an upwards pointing cantilever contact and a downwards pointing cantilever contact. The cantilever contacts are attached to the carrier structure and are arranged around openings in the carrier structure such that the downward pointing cantilevers may reach through the carrier structure. Each contact set defines an independent conductive path between a single pair of opposing chip and test apparatus contacts such that multiple conductive paths are available for each interconnect stage for increased transmission reliability and reduced resistance. The cantilever contacts have a meandering contour and are either combined in symmetrical pairs at their respective tips or are free pivoting. The meandering contour provides a maximum deflectable cantilever length within an available footprint defined by the pitch of the tested chip.
    Type: Grant
    Filed: May 9, 2005
    Date of Patent: May 15, 2007
    Assignee: Antares conTech, Inc.
    Inventors: January Kister, James Jaquette, Steve Fahrner
  • Patent number: 7189092
    Abstract: An interconnect mechanism for providing electrical interconnection between a device under test and a tester includes a base having a first side and a second side. The base defines a plurality of apertures extending from the first side to the second side. The first side of the base is configured to receive the device under test. The interconnect mechanism also includes a plurality of alignment mechanisms configured to be detachably coupled to the first side of the base. The plurality of alignment mechanisms define an area of the first side of the base to receive the device under test when the plurality of alignment mechanisms are coupled to the first side of the base. Each of the plurality of alignment mechanisms includes an adjustment mechanism for adjusting the area of the first side of the base defined by the plurality of alignment mechanisms.
    Type: Grant
    Filed: July 8, 2005
    Date of Patent: March 13, 2007
    Assignee: Antares conTech, Inc.
    Inventor: Lawrence Ercoli Piatti
  • Patent number: 7189078
    Abstract: An interconnect assembly includes a number of interconnects combined in a preferably planar dielectric carrier frame having resilient portions acting as spring members in conjunction with their respective interconnect's rotational displacement during operational contacting. Each interconnect is fabricated as a see-saw structure pivoting around a rotation axis that substantially coincides with a symmetry plane of the torsion features provided by the resilient portion. The torsion features protrude towards and adhere to a central portion of the see-saw interconnect such that an angular movement of the interconnect is resiliently opposed by the torsion feature and the resilient portion. The torsion features and interconnects may be independently optimized to provide the interconnect with maximum stiffness and a maximum deflection at same time.
    Type: Grant
    Filed: March 10, 2005
    Date of Patent: March 13, 2007
    Assignee: Antares conTech, Inc.
    Inventors: January Kister, James Jaquette, Gene Tokraks
  • Patent number: 7064564
    Abstract: A probe apparatus having probe groups comprising two or three probes that independently contact single terminals of tested chips. As a result, the probe apparatus is capable of recognizing voltage drops of a test signal applied prior to the chip testing onto a test path along two or three probes contacting, the terminal and the interfaces between them. The test path does not pass through the chip. An electronic circuit measures the voltage drops and compensated accordingly operational signals passing through the terminals, the probes and the interfaces during the chip testing. A first embodiment comprises two probes per group. A second embodiment comprises three probes per group. In the second embodiment, the variable resistance component of three resistance measurements of first/second, first/third and second/third resistance paths are compared by the electronic circuit, in order to determine absolute resistance values for each of the three signal paths.
    Type: Grant
    Filed: February 1, 2001
    Date of Patent: June 20, 2006
    Assignee: Antares conTech, Inc.
    Inventors: January Kister, Krzysztof Dabrowiecki
  • Patent number: 4038239
    Abstract: The disclosed process for making a high % solids, one-part, curable, essentially flowable or pumpable, high equivalent weight polyurethane (i.e., polyol-polyisocyanate adduct) prepolymer composition involves de-watering the polyol component of the reaction mixture with an alkaline earth metal oxide, preferably calcium oxide; adding the minimum acceptable level of catalyst for the NCO/polyol reaction; exothermically reacting a partially hindered aliphatic polyisocyanate such as isophorone diisocyanate (IPDI) and a partially hindered aromatic polyisocyanate such as 2,4-tolylene diisocyanate seriatim, so that at least about one-fourth of the IPDI reacts before the 2,4-TDI is added; and then adding more catalyst for the curing (e.g. moisture cure) reaction.
    Type: Grant
    Filed: August 19, 1975
    Date of Patent: July 26, 1977
    Assignee: ConTech Inc.
    Inventors: Robert N. Coyner, Peter Skujins
  • Patent number: D525207
    Type: Grant
    Filed: December 2, 2003
    Date of Patent: July 18, 2006
    Assignee: Antares conTech, Inc.
    Inventors: January Kister, James Jaquette, Steve Fahrner