Abstract: A data diode device with specific packet relay function (14) is connected between an external network and an internal network. The data diode device with specific packet relay function (14) includes a first unit (21) and a second unit (22) connected by a signal line (Q), and the first unit (21) connected with the external network (15) has a first reference table (T1) in which a plurality of pieces of packet registration information are registered to correspond to the signal lines (Q). The second unit (22) connected with the internal network (16) has a second reference table (T2) content of which is the same as the first reference table (T1). By activating the signal line corresponding to the packet registration information including a source IP address, a destination IP address and application data which are included in a packet received by the first unit (21), the content of the packet and that the packet to be transmitted to the internal network (16) is received are conveyed to the second unit (22).

Abstract: Arithmetic operation circuits and a verification circuit are formed by loading configuration information into a configuration memory in an FPGA. Arithmetic operation circuits have the same arithmetic operation function, but are different from each other in combination of the circuit blocks. The arithmetic operation circuits are formed by combining the circuit blocks to make the maximum use of the DSP block, while the arithmetic operation circuit is formed by combining the circuit blocks other than DSP block. The arithmetic operation circuits each are configured to use a block RAM as the data hold memory, while the arithmetic operation circuit is configured to use a distributed RAM as the data hold memory. Each of the arithmetic operation circuits receives the input data, and outputs arithmetic operation result data (V1 to V3). A verification circuit compares the arithmetic operation result data to verify whether errors occur.