Patents Assigned to Control System Laboratory Ltd.
  • Patent number: 11442475
    Abstract: An unmanned aircraft 1 according to an embodiment of the present invention provides an unmanned aircraft that properly makes a forced landing in case of an abnormality. The unmanned aircraft 1 is configured as a multicopter that flies with lift and thrust generated by rotation of six rotors 13. The unmanned aircraft 1 identifies a forced landing site in a case of having detected an abnormality during flight and controls motors 12 configured to drive the respective rotors 13, to make a landing at the identified forced landing site. The unmanned aircraft 1 is consequently enabled to make an autonomous forced landing at a specific site in case of an abnormality.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: September 13, 2022
    Assignee: AUTONOMOUS CONTROL SYSTEMS LABORATORY LTD.
    Inventors: Daisuke Iwakura, Yuji Ogawa, Nobuyuki Togashi
  • Publication number: 20210171196
    Abstract: The objective of the present invention is to provide a device configuration, a method and the like for performing an imaging survey within a survey space using an unmanned aerial vehicle. Provided is an unmanned aerial vehicle provided with at least four rotating blades, and a control unit which controls the rotation of the at least four rotating blades, wherein the unmanned aerial vehicle is provided with a survey camera in a position on a chassis of the unmanned aerial vehicle, between at least one rotating blade positioned on the side in the direction of travel, from among the at least four rotating blades, and at least one rotating blade positioned on the opposite side to the direction of travel, and wherein, when flying above a surface in which a liquid is at least partially present, the unmanned aerial vehicle flies while at least partially preventing scattered liquid from reaching above the chassis by means of the at least four rotating blades.
    Type: Application
    Filed: April 10, 2019
    Publication date: June 10, 2021
    Applicants: Autonomous Control Systems Laboratory Ltd., NJS Co., Ltd.
    Inventors: Kenji KUROIWA, Shosuke INOUE, Yusuke INAGAKI, Patrik Ken TAKEUCHI
  • Patent number: 10841132
    Abstract: A data diode device with specific packet relay function (14) is connected between an external network and an internal network. The data diode device with specific packet relay function (14) includes a first unit (21) and a second unit (22) connected by a signal line (Q), and the first unit (21) connected with the external network (15) has a first reference table (T1) in which a plurality of pieces of packet registration information are registered to correspond to the signal lines (Q). The second unit (22) connected with the internal network (16) has a second reference table (T2) content of which is the same as the first reference table (T1). By activating the signal line corresponding to the packet registration information including a source IP address, a destination IP address and application data which are included in a packet received by the first unit (21), the content of the packet and that the packet to be transmitted to the internal network (16) is received are conveyed to the second unit (22).
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: November 17, 2020
    Assignee: Control System Laboratory LTD.
    Inventor: Kenichi Morimoto
  • Publication number: 20200285253
    Abstract: An unmanned aircraft 1 according to an embodiment of the present invention provides an unmanned aircraft that properly makes a forced landing in case of an abnormality. The unmanned aircraft 1 is configured as a multicopter that flies with lift and thrust generated by rotation of six rotors 13. The unmanned aircraft 1 identifies a forced landing site in a case of having detected an abnormality during flight and controls motors 12 configured to drive the respective rotors 13, to make a landing at the identified forced landing site. The unmanned aircraft 1 is consequently enabled to make an autonomous forced landing at a specific site in case of an abnormality.
    Type: Application
    Filed: October 23, 2017
    Publication date: September 10, 2020
    Applicant: Autonomous Control Systems Laboratory Ltd.
    Inventors: Daisuke IWAKURA, Yuji OGAWA, Nobuyuki TOGASHI
  • Publication number: 20200244487
    Abstract: A data diode device with specific packet relay function (14) is connected between an external network and an internal network. The data diode device with specific packet relay function (14) includes a first unit (21) and a second unit (22) connected by a signal line (Q), and the first unit (21) connected with the external network (15) has a first reference table (T1) in which a plurality of pieces of packet registration information are registered to correspond to the signal lines (Q). The second unit (22) connected with the internal network (16) has a second reference table (T2) content of which is the same as the first reference table (T1). By activating the signal line corresponding to the packet registration information including a source IP address, a destination IP address and application data which are included in a packet received by the first unit (21), the content of the packet and that the packet to be transmitted to the internal network (16) is received are conveyed to the second unit (22).
    Type: Application
    Filed: January 4, 2017
    Publication date: July 30, 2020
    Applicants: Control System Laboratory, Ltd., Control System Laboratory, Ltd.
    Inventor: Kenichi Morimoto
  • Patent number: 10067742
    Abstract: Arithmetic operation circuits and a verification circuit are formed by loading configuration information into a configuration memory in an FPGA. Arithmetic operation circuits have the same arithmetic operation function, but are different from each other in combination of the circuit blocks. The arithmetic operation circuits are formed by combining the circuit blocks to make the maximum use of the DSP block, while the arithmetic operation circuit is formed by combining the circuit blocks other than DSP block. The arithmetic operation circuits each are configured to use a block RAM as the data hold memory, while the arithmetic operation circuit is configured to use a distributed RAM as the data hold memory. Each of the arithmetic operation circuits receives the input data, and outputs arithmetic operation result data (V1 to V3). A verification circuit compares the arithmetic operation result data to verify whether errors occur.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: September 4, 2018
    Assignee: Control System Laboratory Ltd.
    Inventor: Kenichi Morimoto