Abstract: An interface device allows communication between a 1394 device and an Ethernet via an 802.3 PHY. To the 1394 link, the device appears as a 1394 PHY, to the 802.3 PHY, the device appears as an 802.3 MAC. The interface device includes a 1394 PHY-link link interface, a Gigabyte Media Independent Interface (GMII), checksum padding and checksum stripping units, emulated 1394 PHY registers, and a clock generation unit. The interface device uses two clocks to supply timing clocks for the 1394 link and for the 802.3 PHY. For speed matching, the interface device matches the data rate of the link (S100, S200, S400, S800) with the PHY (nominally 1 Gbps) using a padding algorithm. The interface device provides the link with management information through a set of IEEE 1394 compatible registers that are accessed through the 1394 interface, emulating a single port 1394 PHY. The interface device also manages the IEEE 802.3 PHY as would a MAC through the MDC/MDIO interface.

Abstract: An integrated module incorporates not only a cable socket, but also a chip carrier for an integrated circuit and a daughter card for discrete components. The module can be mounted on any printed circuit board, within a switch, router, hub or other network device. A network socket, one or more integrated circuits and all discrete components (resistors, capacitors, coil, etc.) are contained within the module. The functionality of a transceiver and a media access controller are split into a digital portion and an analog portion. Each of the digital and analog functionality is implemented on a separate integrated circuit and both integrated circuits are placed next to one another in the chip carrier within the integrated module. Shielding around the socket is extended to surround the entire integrated module. The metal shielding extends underneath the integrated module and contacts the copper base of the chip carrier to serve as a heat sink.

Abstract: Methods and apparatus for efficiently communicating across an asymmetric digital subscriber loop are disclosed. According to one aspect of the present invention, a method for communicating between a computer in a central office and a remote computer across DSL communications links involves sending a first set of data from the central office computer across a first DSL communications link. The first DSL communications link couples the central office computer to a switch. The method also includes selecting a second DSL communications link, which couples the switch and the remote computer, and sending the first set of data from the switch to the remote computer across the second DSL communications link.

Abstract: Disclosed is a queue selection method for performing data transfers. The method includes scaling a system bandwidth into a plurality of scaled bandwidth integers that extend to a maximum scaled system bandwidth integer. Providing a plurality of queues where each of the plurality of queues are associated with a scaled bandwidth integer, and a sum of the scaled bandwidth integers for each of the plurality of queues is less than or equal to the maximum scaled system bandwidth integer. The method further determines an allocated bandwidth integer from the scaled bandwidth integers for each of the plurality of queues that are enabled, and increments a system virtual time upon each cycle of a system clock while at least one of the plurality of queues is enabled. The method then selects one of the plurality of queues having a lowest queue virtual time, and outputs a packet from the selected one of the plurality of queues having the lowest queue virtual time.

Abstract: A transceiver for exchanging data with a transmission channel using any of the 100BaseT2, 100BaseTX, or 100BaseT4 standards, which includes a receive circuit for receiving analog data from the transmission channel. The receive circuit includes a first switch and a first analog-to-digital converter coupled to the first switch. The receive circuit further includes a second analog-to-digital converter coupled to the first switch. There is further included a second switch coupled to the first analog-to-digital converter and to the second analog-to-digital converter. The analog data is switched by the first switch into the first analog-to-digital converter and the second analog-to-digital converter to allow the first analog-to-digital converter and the second analog-to-digital converter to support sampling requirements of any of the 100BaseT2, the 100BaseTX, or the 100BaseT4 standards.