Abstract: A memory device multi-chip package containing conventional parallel bus flash memory dies interfacing to an external parallel bus having the same format and protocol. A bridge chip within the memory device interfaces internally over one or more internal parallel bus interfaces to the flash dies within the package. The bridge chip presents a single load on the external bus interface so that several memory device multi-chip packages (MCPs) can be connected to a controller, thereby increasing the number of flash dies supported by a single controller channel operating at full performance.