Abstract: Implementations relate to a data processor that includes a data processing unit having a plurality of processing elements and a cache hierarchy including a plurality of levels of data caches. The data caches include a first level data cache connected to a second level data cache, and a main memory connected to the highest level cache of the cache hierarchy. At least one of the first level data cache or second level data cache is divided into a plurality of cache segments, and during operation of the data processor, at least some of the plurality of cache segments are excluded from cache operation. Each of the excluded cache segments is dedicated to an associated processing element as tightly coupled local access memory.

Abstract: The present invention relates to a processor having a trace cache and a plurality of ALUs arranged in a matrix, comprising an analyser unit located between the trace cache and the ALUs, wherein the analyser unit analyses the code in the trace cache, detects loops, transforms the code, and issues to the ALUs sections of the code combined to blocks for joint execution for a plurality of clock cycles.

Abstract: Implementations relate to a data processor that includes a data processing unit having a plurality of processing elements and a cache hierarchy including a plurality of levels of data caches. The data caches include a first level data cache connected to a second level data cache, and a main memory connected to the highest level cache of the cache hierarchy. At least one of the first level data cache or second level data cache is divided into a plurality of cache segments, and during operation of the data processor, at least some of the plurality of cache segments are excluded from cache operation. Each of the excluded cache segments is dedicated to an associated processing element as tightly coupled local access memory.

Abstract: The present invention relates to a processor having a trace cache and a plurality of ALUs arranged in a matrix, comprising an analyser unit located between the trace cache and the ALUs, wherein the analyser unit analyses the code in the trace cache, detects loops, transforms the code, and issues to the ALUs sections of the code combined to blocks for joint execution for a plurality of clock cycles.

Abstract: A wearable device and system has been developed to help users learn the practices of diaphragmatic breathing and breathing patterns to improve running and walking performance. The wearable has a breathing sensor (breathe in-breathe out) and a movement sensor used to identify foot strikes. A processor computes the number of foot strikes occurring while inhaling and the number of foot strikes occurring while exhaling to report breathing patterns as a function of time. The algorithms may be modified to teach breathing patterns to athletes in other sports and deep breathing for numerous movement and minimal movement applications.

Abstract: The invention relates to a method for processing instructions out-of-order on a processor comprising an arrangement of execution units. The inventive method comprises looking up operand sources in a Register Positioning Table and setting operand input references of the instruction to be issued accordingly, checking for an Execution Unit (EXU) available for receiving a new instruction, and issuing the instruction to the available Execution Unit and entering a reference of the result register addressed by the instruction to be issued to the Execution Unit into the Register Positioning Table (RPT).

Abstract: Implementations relate to a data processor that includes a data processing unit having a plurality of processing elements and a cache hierarchy including a plurality of levels of data caches. The data caches include a first level data cache connected to a second level data cache, and a main memory connected to the highest level cache of the cache hierarchy. At least one of the first level data cache or second level data cache is divided into a plurality of cache segments, and during operation of the data processor, at least some of the plurality of cache segments are excluded from cache operation. Each of the excluded cache segments is dedicated to an associated processing element as tightly coupled local access memory.

Abstract: A system includes companion device that has movement sensors and a separate wearable device that has core contraction sensors. The companion device can be coupled to moving objects such as exercise equipment. Signals from the companion device and wearable device sensors are transmitted to a processor which analyzes the object movement signals and determines when a qualifying movement is performed which benefits from core contraction. Signals from the core contraction sensors are also transmitted to the processor and are used to determine if the core is contracted during the qualifying movement. If the core is contracted during the qualifying movement, the movement is a protected qualifying movement. However, if the core is not contracted during the qualifying movement the movement is an unprotected qualifying movement. The system can inform the user when unprotected qualifying movements are performed.

Abstract: A single chip sequential processor comprising at least one ALU-Block, where said sequential processor is capable of maintaining its op-codes while processing data such as to overcome the necessity of requiring a new instruction in every clock cycle.

Abstract: The present invention relates to a processor having a trace cache and a plurality of ALUs arranged in a matrix, comprising an analyser unit located between the trace cache and the ALUs, wherein the analyser unit analyses the code in the trace cache, detects loops, transforms the code, and issues to the ALUs sections of the code combined to blocks for joint execution for a plurality of clock cycles.

Abstract: A wearable device has a core contraction sensor. Signals from the core contraction sensor are transmitted to a processor which analyzes the core contraction signals and determines if the user's core is contracted or relaxed. The processor can cause a computing device to output a sequence of tones in response to a core contraction signal. The sequence of tones can correspond to a song which can be played by performing a plurality of core contractions with durations that correspond to a duration of the notes in the song. Alternatively, the core muscles can be contracted to correspond to music heard by the user. The processor can output a score based upon the matching of the core contractions with the musical notes.

Abstract: A wearable device and system has been developed to provide feedback to help users be able to engage specific muscle groups on cue, effectively exercise said muscle groups, and learn to engage said muscle groups before and through movements. Algorithms for identifying relaxed-to-engaged and engaged-to-relaxed transitions may be important for providing a positive user experience. The wearable device and system may be used for training effective use of the core and other muscles. A myokinesiometer is described to display target muscle engagement and body movement data simultaneously. The myokinesiometer facilitates specifying tests for protected and unprotected movement analyses.

Abstract: A single chip sequential processor comprising at least one ALU-Block, where said sequential processor is capable of maintaining its op-codes while processing data such as to overcome the necessity of requiring a new instruction in every clock cycle.

Abstract: Systems and methods are provided to assist in different forms of communication using messaging platforms such as email, text messaging, etc. For instance, an improved massaging platform is provided for creating better human to human communication and organization of messaging, as well as messaging involving machines. Human to human include, for example, emails, text messages, social media messages, or other forms of electronic communication from another human, which usually requires some sort of response back from another user. Aspects are provided herein for highlighting and distinguishing such forms of communication, and to provide interfaces and tools to organize and simplify such interactions.

Abstract: The present invention relates to a method for compiling code for a multi-core processor, comprising: detecting and optimizing a loop, partitioning the loop into partitions executable and mappable on physical hardware with optimal instruction level parallelism, optimizing the loop iterations and/or loop counter for ideal mapping on hardware, chaining the loop partitions generating a list representing the execution sequence of the partitions.

Abstract: A processor including an instruction fetcher to fetch instructions, a decoder to decode the instructions, at least one load unit adapted to load data, at least one execution unit adapted to perform arithmetic computations on the data by executing the fetched and decoded instructions, a register file adapted to store results of the arithmetic computations, and a multiplexer arrangement provided such that one or more units of the execution unit selectively obtain operands from one of: the register file or a unit used for arithmetic computation of a preceding instruction. The processor is adapted to process and execute the instructions such that processing of the instructions is started under the following conditions: the execution unit is ready for instruction execution, and data from the at least one load unit is available to the at least one execution unit.

Abstract: A single chip sequential processor comprising at least one ALU-Block, where said sequential processor is capable of maintaining its op-codes while processing data such as to overcome the necessity of requiring a new instruction in every clock cycle.

Abstract: A wearable device has a core contraction sensor and a movement sensor which transmits signals to a processor which analyzes the signals and uses the data to control aspects of a video game. The core contraction signal may determine if the user's core is contracted or relaxed. A video game may be used with the wearable device to encourage usage of the core muscles with the player getting points or rewards for engaging their core muscles and properly timing the engagement of the core muscles with body movements. The wearable device may be used in place of, or together with conventional video game control devices. Developing the habit of using the core muscles during may be beneficial in back pain rehab and prevention, fitness training and wellness, athletic performance improvement, and reducing workplace injuries in occupations involving heavy lifting.

Abstract: The system includes a movement sensor and a core contraction sensor in communication with a processor. The core contraction sensor is placed on the core muscles of a user and transmits core contraction signals to the processor. The processor receives movement signals from the movement sensor and identifies user movements that are qualifying movements that benefit from core contractions. The processor also monitors the timing between the qualifying movements and the core contractions to identify protected and unprotected qualifying movements. The system can also include a memory for storing core scores that are calculated from the protected and unprotected qualifying movements, exercise information and core sensor calibration information. The core contraction information can be used to calibrate the core contraction sensor. The core contraction and movement information can be transmitted to a therapist who can monitor the user's activities and provide instructional feedback.

Abstract: The invention relates to a multi-core processor memory system, wherein it is provided that the system comprises memory channels between the multi-core processor and the system memory, and that the system comprises at least as many memory channels as processor cores, each memory channel being dedicated to a processor core, and that the memory system relates at run-time dynamically memory blocks dedicatedly to the accessing core, the accessing core having dedicated access to the memory bank via the memory channel.