Abstract: The present invention provides a refresh clock generator which optimally controls a period of a refresh clock signal according to temperature variation and outputs the refresh clock signal. The refresh clock generator includes a bias voltage generating unit for generating first and second bias voltages in response to a temperature variation and a clock generator for generating a refresh clock signal having a frequency which is controlled or adjusted based on the first and second bias voltages, wherein the first bias voltage is varied in proportion to the temperature variation; the second bias voltage is varied in inverse proportion to the temperature variation; and the frequency of the refresh clock signal is varied in proportion to the temperature variation.

Abstract: An apparatus for a refresh and a data input device in the SRAM having a storage capacitor cell comprises an internal clock generator for generating and outputting two internal clock signals having a certain time difference of each other, a refresh timer for generating and outputting an output signal to notify a refresh time, a refresh signal generator for generating a refresh signal in response to a faster signal of the two internal signals and the output signal from the refresh timer, a refresh counter for generating refresh addresses during the refresh and a column path controller for controlling the activation of a column path in response to a row active signal and the refresh signal.

Abstract: Disclosed is an address input apparatus of a semiconductor memory device having a unit cell including a capacitor, comprising an internal clock generator for generating and outputting an internal clock signal at a fixed period and a buffering and sampling unit for buffering an inputted address and sampling the address in the fixed period in response to the internal clock signal.