Abstract: The present invention provides a system and method that includes a library module including a plurality of programmable components and at least one corresponding test case for each programmable component. The system also includes the configurator module coupled to the library module and accessing at least one of the plurality of programmable components and the at least one corresponding test case. The configurator module further outputs a code describing a processor for running a software-defined digital signal processor and includes the accessed programmable component and a plurality of interconnections linking the accessed programmable component. The system further includes a test case generator coupled to the configurator to output a test suite including the at least one corresponding test case for each accessed programmable component and a plurality of interconnect tests to test the plurality of interconnections linking the accessed programmable component.

Abstract: A programmable digital signal processor includes a plurality of memory units, a plurality of accelerator units and a processor core. The digital signal processor also includes a programmable network that may be configured to selectively provide connectivity between the memory units, the accelerator units, and the processor core. Each of the accelerator units may be configured to perform one or more dedicated functions. The processor core may include an execution unit that may be configured to execute instructions that are associated with datapath flow control. The programmable network may be configured to selectively provide the connectivity in response to execution of particular instructions.

Abstract: A programmable digital signal processor including a clustered SIMD microarchitecture includes a plurality of accelerator units, a processor core and a complex computing unit. Each of the accelerator units may be configured to perform one or more dedicated functions. The processor core includes an integer execution unit that may be configured to execute integer instructions. The complex computing unit may be configured to execute complex vector instructions. The complex computing unit may include a first and a second clustered execution pipeline. The first clustered execution pipeline may include one or more complex arithmetic logic unit datapaths configured to execute first complex vector instructions. The second clustered execution pipeline may include one or more complex multiplier accumulator datapaths configured to execute second complex vector instructions.