Abstract: A host fabric adapter is disclosed. Embodiments include a high-speed serial expansion bus and at least two fabric ports configured to receive links from corresponding ports of at least two switches, each of which comprise corresponding switches in parallel and independent topologies. The host fabric adapter includes at least two packet processing pipelines configured for reception and transmission of packets through the fabric ports; a PCIe switch configured to receive a packet on the expansion bus and select a pipeline for transmission and configured to receive a packet from one of the pipelines and transmit the packet on the expansion bus. The host fabric adapter also includes a fabric switch configured to receive a packet from one of the fabric ports and select a pipeline for transmission to the PCIe switch and to receive a packet on one of the pipelines; and select one of the fabric ports for transmission of the packet on the fabric.

Abstract: A sacrificial mode of link operation during link negotiation and initialization is provided. Embodiments include transmitting (804), by a link manager (402) of a switch (102) in a high-performance computing system, a sacrificial mode parameter (808) for the local link manager (402), receiving (806), by the link manager (402), a sacrificial mode parameter (820) for a link partner, establishing (816), by the link manager (402), a local sacrificial period (818) in dependence upon the local sacrificial mode parameter (808) and the received sacrificial mode parameter (820) of the link partner; and operating (822) one or more ports in sacrificial mode for the sacrificial period (818) including suspending error correction during sacrificial mode.

Abstract: An autonomous and integrated translator for local server bus operations is provided. The translator comprises encapsulation logic and decapsulation logic. The encapsulation logic encapsulates transactions for local server bus operations with fabric-switched header and trailer information and the decapsulation logic decapsulates the header and trailer information.

Abstract: A switch is provided for routing packets in an interconnection network. The switch includes a plurality of egress ports to transmit packets and one or more ingress ports to receive packets. The switch also includes a network capacity circuit for obtaining network capacity for transmitting packets via the plurality of egress ports. The switch also includes a port sequence generation circuit configured to generate a port sequence that defines a pseudo-randomly interleaved sequence of a plurality of path options via the plurality of egress ports, based on the network capacity. The switch also includes a routing circuit for routing one or more packets, received from the one or more ingress ports, towards a destination, based on the port sequence.

Abstract: A switch is provided for routing packets in an interconnection network. The switch includes a plurality of egress ports to transmit packets. The switch also includes one or more ingress ports to receive packets. The switch also includes a port and bandwidth capacity circuit configured to obtain (i) port capacity for a plurality of egress ports of the switch, and (ii) bandwidth capacity for transmitting packets to a destination. The switch also includes a network capacity circuit configured to compute network capacity, for transmitting packets to the destination, via the plurality of egress ports, based on a function of the port capacity and the bandwidth capacity. The switch also includes a routing circuit configured to route one or more packets received via one or more ingress ports of the switch, to the destination, via the plurality of egress ports, based on the network capacity.

Abstract: A switch is provided for routing packets in an interconnection network. The switch includes egress ports to transmit packets, and ingress ports to receive packets. The switch also includes a buffer capacity circuit configured to obtain local buffer capacity for buffers configured to buffer packets transmitted via the switch. The switch also includes a telemetry circuit configured to receive telemetry flow control units from next switches coupled to the switch. Each telemetry flow control unit corresponds to buffer capacity at a respective next switch. The switch also includes a network capacity circuit configured to compute network capacity for transmitting packets to a destination based on the telemetry flow control units and the local buffer capacity. The switch also includes a routing circuit configured to receive packets via the ingress ports, and route the packets to the destination, via the egress ports, with bandwidth proportional to the network capacity.

Abstract: A switch is provided for routing packets in an interconnection network. The switch includes egress ports to transmit packets, and ingress ports to receive packets. The switch also includes a buffer capacity circuit configured to obtain local buffer capacity for buffers configured to buffer packets transmitted via the switch. The switch also includes a telemetry circuit configured to receive telemetry flow control units from next switches coupled to the switch. Each telemetry flow control unit corresponds to buffer capacity at a respective next switch. The switch also includes a network capacity circuit configured to compute network capacity for transmitting packets to a destination based on the telemetry flow control units and the local buffer capacity. The switch also includes a routing circuit configured to receive packets via the ingress ports, and route the packets to the destination, via the egress ports, with bandwidth proportional to the network capacity.

Abstract: A mirrored switch configuration is presented. The switch configuration includes at least two switches, each having corresponding baseline bandwidths and corresponding radix, and port configurations; a plurality of links, and a host fabric interface adapter (‘HFA’) including an interconnect adapted to receive, from corresponding ports of the at least two switches, one link from one port of one of the at least two switches and one link from a corresponding port of another of the at least two switches.

Abstract: Creating a high-performance computing environment including a plurality of switches and a plurality of cables connecting the switches in a cyclic topology is provided. Embodiments include determining the number of virtual routing groups (‘VRGs’) for the cyclic topology, assigning each VRG a unique VRG identifier (‘VRG ID’); assigning to each VRG a plurality of switches; establishing, through at least one switch in each VRG, a cyclic connection with every other VRG in the topology wherein a cyclic connection is formed by connecting one switch from each VRG in a cyclic set of VRGs to the same switch in every other VRG in the cyclic set and wherein the VRGs are connected to one another according to a set of square matrices of VRGs.

Abstract: Routing in a multi-computer network comprising a plurality of multi-switch virtual router groups (‘VRGs’) interconnected by only cyclic connections among the VRGs is provided. A cyclic connection is formed by connecting one switch from each VRG in a cyclic set of VRGs to the same switch in every other VRG in the cyclic set and each switch in the cyclic set is connected in an all-to-all configuration. Every VRG in the network has at least one cyclic connection with every other VRG in the network. Embodiments include selecting a non-minimal path between a source VRG and a destination VRG in a cyclic set that passes through only one switch in a pass-through VRG in the cyclic set; and sending packets from the source VRG in the cyclic set to the destination VRG through the one switch in the pass-through VRG.

Abstract: Methods, systems, and switches for burst error correction of packets in a high-performance computing (‘HPC’) environment are provided. Embodiments include receiving, at a switch, one or more packets and one or more codewords associated with the one or more packets; determining, by the switch in dependence upon a link-level replay latency algorithm, whether forward error correction has higher latency than a link-level replay; and if link-level replay has less latency than forward error correction, requesting, by the switch, a link-level replay; and using forward error correction if forward error correction has less latency.

Abstract: Methods, systems, and products for static dispersive routing of packets in a high-performance computing (‘HPC’) environment are provided. Embodiments include generating an entropy value; receiving, by a switch, a plurality of packets, where each packet includes a header with the entropy value and a destination local identifier (‘DLID’) value; and routing, by the switch in dependence upon the entropy value and the DLID value, the packets to a next switch in order.

Abstract: A switch is provided for routing packets in an interconnection network. The switch includes a plurality of egress ports to transmit packets. The switch also includes one or more ingress ports to receive packets. The switch also includes a port and bandwidth capacity circuit configured to obtain (i) port capacity for a plurality of egress ports of the switch, and (ii) bandwidth capacity for transmitting packets to a destination. The switch also includes a network capacity circuit configured to compute network capacity, for transmitting packets to the destination, via the plurality of egress ports, based on a function of the port capacity and the bandwidth capacity. The switch also includes a routing circuit configured to route one or more packets received via one or more ingress ports of the switch, to the destination, via the plurality of egress ports, based on the network capacity.

Abstract: A switch is provided for routing packets in an interconnection network. The switch includes a plurality of egress ports to transmit packets. The switch also includes one or more ingress ports to receive packets. The switch also includes a port and bandwidth capacity circuit configured to obtain (i) port capacity for a plurality of egress ports of the switch, and (ii) bandwidth capacity for transmitting packets to a destination. The switch also includes a network capacity circuit configured to compute network capacity, for transmitting packets to the destination, via the plurality of egress ports, based on a function of the port capacity and the bandwidth capacity. The switch also includes a routing circuit configured to route one or more packets received via one or more ingress ports of the switch, to the destination, via the plurality of egress ports, based on the network capacity.

Abstract: A switch is provided for routing packets in an interconnection network. The switch includes egress ports to transmit packets, and ingress ports to receive packets. The switch also includes a buffer capacity circuit configured to obtain local buffer capacity for buffers configured to buffer packets transmitted via the switch. The switch also includes a telemetry circuit configured to receive telemetry flow control units from next switches coupled to the switch. Each telemetry flow control unit corresponds to buffer capacity at a respective next switch. The switch also includes a network capacity circuit configured to compute network capacity for transmitting packets to a destination based on the telemetry flow control units and the local buffer capacity. The switch also includes a routing circuit configured to receive packets via the ingress ports, and route the packets to the destination, via the egress ports, with bandwidth proportional to the network capacity.

Abstract: A switch is provided for routing packets in an interconnection network. The switch includes a plurality of egress ports to transmit packets. The switch also includes one or more ingress ports to receive packets. The switch also includes a port and bandwidth capacity circuit configured to obtain (i) port capacity for a plurality of egress ports of the switch, and (ii) bandwidth capacity for transmitting packets to a destination. The switch also includes a network capacity circuit configured to compute network capacity, for transmitting packets to the destination, via the plurality of egress ports, based on a function of the port capacity and the bandwidth capacity. The switch also includes a routing circuit configured to route one or more packets received via one or more ingress ports of the switch, to the destination, via the plurality of egress ports, based on the network capacity.