Abstract: A computer comprising one or more processors and memory may implement multiple threads that perform a lock operation using a data structure comprising an allocation field and a grant field. Upon entry to a lock operation, a thread allocates a ticket by atomically copying a ticket value contained in the allocation field and incrementing the allocation field. The thread compares the allocated ticket to the grant field. If they are unequal, the thread determines a number of waiting threads. If the number is above the threshold, the thread enters a long term wait operation comprising determining a location for long term wait value and waiting on changes to that value. If the number is below the threshold or the long term wait operation is complete, the thread waits for the grant value to equal the ticket to indicate that the lock is allocated.

Abstract: A method for applying RF power in a plasma process chamber is provided, including: generating a first RF signal; generating a second RF signal; generating a third RF signal; wherein the first, second, and third RF signals are generated at different frequencies; combining the first, second and third RF signals to generate a combined RF signal, wherein a wave shape of the combined RF signal is configured to approximate a sloped square wave shape; applying the combined RF signal to a chuck in the plasma process chamber.

Abstract: Systems, methods, and apparatuses relating to circuitry to implement toggle point insertion for a clustered decode pipeline are described.

Abstract: There is provided a technique that includes: (a) supplying a first gas containing a group XIV element to a substrate on which a film containing the group XIV element is formed such that reaction by-products generated by reaction with the group XIV element contained in the film formed on the substrate are saturated and adsorbed on the substrate; (b) supplying a second gas containing a halogen after (a); and (c) etching the film containing the group XIV element formed on the substrate by alternately repeating (a) and (b).

Abstract: A computer-implemented method for a service framework to develop application services, including: providing at least one module of a module stack to a client; determining if the provided module has been modified by the client; determining dependency data, at least including information on the dependency of further modules of the module stack from the provided module; and providing the dependency data of the other modules of the module stack from the provided module.

Abstract: A mold die includes a resin injection gate through which fluid resin serving as mold resin is injected toward a cavity, a resin reservoir to store the fluid resin flowing through the cavity, and a resin reservoir gate. The resin reservoir is provided on the side opposite to the side on which the resin injection gate is arranged with the cavity interposed. The resin reservoir gate communicatively connects the cavity and the resin reservoir. The opening cross-sectional area of the resin reservoir gate is smaller than the opening cross-sectional area of the resin injection gate.

Abstract: Techniques for implementing an infrastructure orchestration service are described. A configuration file for a deployment to a first execution target and a second execution target can be received. A first safety plan can be generated for the first execution target that comprises a first list of resources and operations associated with deployment at the first execution target. Approval of the first safety plan can be received. A second safety plan can be generated for the second execution target that comprises a second list of resources and operations associated with deployment at the second execution target. A determination can be made whether the second safety plan is a subset of the first safety plan. If the determination is that the second safety plan is a subset of the first safety plan, the second safety plan can automatically be approved and transmitted to the second execution target for deployment.

Abstract: A first light receiving element according to an embodiment of the present disclosure includes a plurality of pixels, a photoelectric converter that is provided as a layer common to the plurality of pixels, and contains a compound semiconductor material, and a first electrode layer that is provided between the plurality of pixels on light incident surface side of the photoelectric converter, and has a light-shielding property.

Abstract: Provided is a card reader part. The card reader part has a shell inside which a card carrying passage for carrying a card in a first direction perpendicular to a thickness direction of the card and a carrying mechanism are disposed, the card carrying passage has an opening provided at an end face of the shell on one side in the first direction where a bezel with a card inlet and outlet is mounted, a pressing part is disposed inside the shell, the pressing part abuts against the card from one side in a second direction perpendicular to the thickness direction of the card and the first direction, and in an entire preset region of the card carrying passage from the opening to the other side in the first direction with respect to the opening, the pressing part is provided so as to be separated from the card.

Abstract: Low leakage thin film capacitors for decoupling, power delivery, integrated circuits, related systems, and methods of fabrication are disclosed. Such thin film capacitors include a titanium dioxide dielectric and one or more noble metal oxide electrodes. Such thin film capacitors are suitable for high voltage applications and provide low current density leakage.

Abstract: Systems and methods for providing an improved lamp mode for an imaging device. The imaging device may include an image sensor; an illumination source; and a processing assembly communicatively coupled to the image sensor and the illumination source, and the processing assembly may be configured to: responsive to a scanning event trigger, cause the imaging device to enter a first illumination mode, wherein, in the first illumination mode, a first activation duration of the illumination source is synchronized with an image frame rate of the image sensor to capture image data at the image sensor for indicia decoding; and responsive to sensing an external signal at the imaging device, cause the imaging device to enter or exit a second illumination mode, wherein, in the second illumination mode, a second activation duration of the illumination source is greater than the first activation duration.

Abstract: A silicon carbide semiconductor device includes, on a front surface of a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, a first semiconductor region of the first conductivity type selectively provided on a first side of the third semiconductor layer opposite to a second side thereof facing the silicon carbide semiconductor substrate, second semiconductor regions of the second conductivity type that have an impurity concentration higher than that of the second semiconductor layer, trenches, gate electrodes provided via gate insulating films, an interlayer insulating film, a first electrode, and a second electrode. The first semiconductor region is thinner than a portion of the third semiconductor layer between the first semiconductor region and the second semiconductor layer.

Abstract: A method is presented for attaining different gate threshold voltages across a plurality of field effect transistor (FET) devices without patterning between nanosheet channels. The method includes forming a first set of nanosheet stacks having a first intersheet spacing, forming a second set of nanosheet stacks having a second intersheet spacing, where the first intersheet spacing is greater than the second intersheet spacing, depositing a high-k (HK) layer within the first and second nanosheet stacks, depositing a material stack that, when annealed, creates a crystallized HK layer in the first set of nanosheet stacks and an amorphous HK layer in the second nanosheet stacks, depositing a dipole material, and selectively diffusing the dipole material into the amorphous HK layer of the second set of nanosheet stacks to provide the different gate threshold voltages for the plurality of FET devices.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having germanium-based channels are described. In an example, an integrated circuit structure includes a fin having a lower silicon portion, an intermediate germanium portion on the lower silicon portion, and a silicon germanium portion on the intermediate germanium portion. An isolation structure is along sidewalls of the lower silicon portion of the fin. A gate stack is over a top of and along sidewalls of an upper portion of the fin and on a top surface of the isolation structure. A first source or drain structure is at a first side of the gate stack. A second source or drain structure is at a second side of the gate stack.

Abstract: A semiconductor device includes a power module, a circuit package, and a joint portion joining the power module and the circuit package. The circuit package includes a semiconductor element, a wiring layer electrically connected with the semiconductor element, a heat conductive member, and a second mold resin portion sealing the semiconductor element and the heat conductive member. The wiring layer includes a connecting portion connected with the heat conductive member. One of the connecting portion or the heat conductive member is joined with a signal wire in the power module via the joint portion. The heat conductive member penetrates the second mold resin portion in a thickness direction of the semiconductor element. The heat conductive member and the connecting portion are arranged in a straight line in the thickness direction of the semiconductor element.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A gate dielectric layer is over the top of the fin and laterally adjacent the sidewalls of the fin. A gate electrode is over the gate dielectric layer over the top of the fin and laterally adjacent the sidewalls of the fin. First and second semiconductor source or drain regions are adjacent the first and second sides of the gate electrode, respectively. First and second trench contact structures are over the first and second semiconductor source or drain regions, respectively, the first and second trench contact structures both comprising a U-shaped metal layer and a T-shaped metal layer on and over the entirety of the U-shaped metal layer.

Abstract: A power switch module includes a semiconductor die and a conductive busbar. The semiconductor die is electrically conductively mounted to the busbar. The module also includes a dielectric coolant fluid and the busbar and the semiconductor die mounted thereto are immersed in the dielectric coolant fluid. The module can be include in a power converter assembly.

Abstract: A semiconductor device includes: a first electrode; a first semiconductor layer on the first electrode in a diode region; a second semiconductor layer on the first electrode in an IGBT region; a semiconductor layer on the first and second semiconductor layers, a first upper layer of the semiconductor layer in the diode region including a first region adjacent to the IGBT region and a second region separated from the IGBT region, an impurity concentration being less in the first region than in the second region; a third semiconductor layer on the semiconductor layer; a fourth semiconductor layer of the third semiconductor layer in the IGBT region; a third electrode extending in a direction from the fourth semiconductor layer toward the semiconductor layer; and an insulating film between the second electrode and each of the third semiconductor layer, the semiconductor layer, and the third electrode.

Abstract: Processes and structures resulting therefrom for the improvement of high speed signaling integrity in electronic substrates of integrated circuit packages, which is achieved with the formation of airgap structures within dielectric material(s) between adjacent conductive routes that transmit/receive electrical signals, wherein the airgap structures decrease the capacitance and/or decrease the insertion losses in the dielectric material used to form the electronic substrates.

Abstract: A method for manufacturing an image display device includes: providing a semiconductor growth substrate comprising a semiconductor layer on a first substrate, the semiconductor layer comprising a light-emitting layer; providing a second substrate comprising a circuit, wherein the circuit comprises a circuit element; forming a light-shielding layer on the second substrate; forming an insulating film on the light-shielding layer; bonding the semiconductor layer to the second substrate on which the insulating film is formed; forming a light-emitting element by etching the semiconductor layer; forming an insulating layer that covers the light-emitting element; and electrically connecting the light-emitting element to the circuit element. The light-shielding layer is located between the light-emitting element and the circuit element. In a plan view, the light-shielding layer covers the circuit element.