Abstract: Disclosed is a semiconductor device including a memory hub with a chiplet structure. The semiconductor device includes an interposer, a processor unit placed on the interposer, at least one memory hub placed on the interposer and provided to be physically separated from the processor unit, and at least one memory provided to be physically separated from the memory hub.

Abstract: Disclosed is a semiconductor device including a memory hub with a chiplet structure. The semiconductor device includes an interposer, a processor unit placed on the interposer, at least one memory hub placed on the interposer and provided to be physically separated from the processor unit, and at least one memory provided to be physically separated from the memory hub.

Abstract: There may be provided an interactive DRAM signal analyzer, including a signal input/output unit configured to receive a command signal and data that are transmitted by a system on chip (SoC) including at least one processor through a memory subsystem, a signal analysis processing unit configured to generate a calibration command based on the analysis of the command signal and data that have been received from the memory subsystem, and a DRAM model configured to operate like DRAM based on the command signal and data received from the signal analysis processing unit and to output a command signal and data.

Abstract: Provided is a memory resource sharing system including a first memory, a first memory subsystem configured to identify and distribute resources of the first memory and to control data transmission of the first memory, and a first processor unit including a first processor connected to the first memory subsystem, a second memory, a second memory subsystem configured to identify and distribute resources of the second memory and to control data transmission of the second memory, and a second processor unit including a second processor connected to the second memory subsystem, wherein the first memory subsystem and the second memory subsystem are communicatively connected to each other through a memory bus.

Abstract: Provided is a memory resource sharing system including a first memory, a first memory subsystem configured to identify and distribute resources of the first memory and to control data transmission of the first memory, and a first processor unit including a first processor connected to the first memory subsystem, a second memory, a second memory subsystem configured to identify and distribute resources of the second memory and to control data transmission of the second memory, and a second processor unit including a second processor connected to the second memory subsystem, wherein the first memory subsystem and the second memory subsystem are communicatively connected to each other through a memory bus.