Abstract: A multiple processor (CPU) computer system, each CPU having a separate, local, random access memory means to which it has direct access. An interprocessor bus couples the CPUs to memories of all the CPUs, so that each CPU can access both its own local memory means and the local memories of the other CPUs. A run queue data structure holds a separate run queue for each of the CPUs. Whenever a new process is created, one of the CPUs is assigned as its home site and the new process is installed in the local memory for the home site.

Abstract: There is described a memory system for use in a data processing system having more than one bit mapped display station. The memory system uses a single memory array for storing at least one separate full screen of bit mapped video data for each display station. A single video controller controls the process by which video data is read from the memory array and then simultaneously transmitted to each of the display stations. Furthermore, a memory access control unit coordinates use of the memory by the video controller and the data processing unit and also translates address signals generated by the data processing unit so that it can access the video data for each display station using a contiguous set of address values.