Abstract: A virtual fabrication environment for semiconductor device fabrication that includes an analytics module for performing key parameter identification, process model calibration and variability analysis is discussed.

Abstract: A virtual fabrication environment for semiconductor device structures that includes the use of virtual metrology measurement data to optimize a virtual fabrication sequence is described. Further, calibration of the virtual fabrication environment is performed by comparing virtual metrology measurement data from a virtual fabrication run with a subset of measurements performed in a physical fabrication environment. Additionally, virtual experiments conducted in the virtual fabrication environment of the present invention generate multiple device structure models using ranges of process and design parameter variations for an integrated process flow and design space of interest.

Abstract: Systems and methods for performing depth-dependent oxidation modeling and depth-dependent etch modeling in a virtual fabrication environment are discussed. More particularly, a virtual fabrication environment models, as part of a process sequence, oxidant dispersion in a depth-dependent manner and simulates the subsequent oxidation reaction based on the determined oxidant thickness along an air/silicon interface. Further the virtual fabrication environment performs depth-dependent etch modeling as part of a process sequence to determine etchant concentration and simulate the etching of material along an air/material interface.

Abstract: Systems and methods for performing depth-dependent oxidation modeling and depth-dependent etch modeling in a virtual fabrication environment are discussed. More particularly, a virtual fabrication environment models, as part of a process sequence, oxidant dispersion in a depth-dependent manner and simulates the subsequent oxidation reaction based on the determined oxidant thickness along an air/silicon interface. Further the virtual fabrication environment performs depth-dependent etch modeling as part of a process sequence to determine etchant concentration and simulate the etching of material along an air/material interface.

Abstract: A six transistor SRAM memory cell design is discussed. An SRAM memory cell includes criss-crossed transistors in cross-coupled inverters to achieve a more compact form factor and simplify fabrication.

Abstract: A virtual fabrication environment for semiconductor device fabrication that includes an analytics module for performing key parameter identification, process model calibration and variability analysis is discussed.

Abstract: A virtual fabrication environment for semiconductor device structures that includes the use of virtual metrology measurement data to optimize a virtual fabrication sequence is described. Further, calibration of the virtual fabrication environment is performed by comparing virtual metrology data generated from a virtual fabrication run with a subset of measurements performed in a physical fabrication environment. Additionally, virtual experiments conducted in the virtual fabrication environment of the present invention generate multiple device structure models using ranges of process and design parameter variations for an integrated process flow and design space of interest.

Abstract: A virtual fabrication environment for semiconductor device structures that includes the use of virtual metrology measurement data to optimize a virtual fabrication sequence is described. Further, calibration of the virtual fabrication environment is performed by comparing virtual metrology data generated from a virtual fabrication run with a subset of measurements performed in a physical fabrication environment. Additionally, virtual experiments conducted in the virtual fabrication environment of the present invention generate multiple device structure models using ranges of process and design parameter variations for an integrated process flow and design space of interest.

Abstract: Systems and methods for multi-material mesh generation from fill-fraction voxel model data are discussed. Voxel representations of model data are used to generate robust and accurate multi-material meshes. More particularly, a mesh generation pipeline in a virtual fabrication environment is described that robustly generates high-quality triangle surface and tetrahedral volume meshes from multi-material fill-fraction voxel data. Multi-material topology is accurately captured while preserving characteristic feature edges of the model.

Abstract: A virtual fabrication environment for semiconductor device fabrication that determines a lowest lithography exposure dose range in which one or more defects are still reparable by deposition and etch operations is discussed. Further techniques for repairing line edge roughness caused by lithography are described.

Abstract: Modeling of electrical behavior during the virtual fabrication of a semiconductor device structure is discussed. Electrical behavior occurring in a designated region of a semiconductor device structure may be determined during the virtual fabrication process. For example, resistance or capacitance values may be determined within a modeling domain of interest.

Abstract: A virtual fabrication environment for semiconductor device structures that includes the use of virtual metrology measurement data to optimize a virtual fabrication sequence is described. Further, calibration of the virtual fabrication environment is performed by comparing virtual metrology data generated from a virtual fabrication run with a subset of measurements performed in a physical fabrication environment. Additionally, virtual experiments conducted in the virtual fabrication environment of the present invention generate multiple device structure models using ranges of process and design parameter variations for an integrated process flow and design space of interest.

Abstract: The modeling of a DSA step within a virtual fabrication process sequence for a semiconductor device structure is discussed. A 3D model is created by the virtual fabrication that represents and depicts the possible variation that can result from applying the DSA step as part of the larger fabrication sequence for the semiconductor device structure of interest. Embodiments capture the relevant behavior caused by polymer segregation into separate domains thereby allowing the modeling of the DSA step to take place with a speed appropriate for a virtual fabrication flow.

Abstract: Improving semiconductor device fabrication by enabling the identification and modeling of pattern dependent effects of fabrication processes is discussed. In one embodiment a local mask is generated from a 3-D model of a semiconductor device structure that was created in a 3-D virtual semiconductor fabrication environment from 2-D design layout data and a fabrication process sequence. The local mask is combined with a global mask based on the original design layout data to create a combined mask. The combined mask is convolved with at least one proximity function to generate a loading map which may be used to modify the behavior of one or more processes in the process sequence. This behavior modification enables the 3-D virtual semiconductor fabrication environment to deliver more accurate 3-D models that better predict the 3-D device structure when performing the virtual semiconductor device fabrication that serves as a prelude to physical fabrication.

Abstract: A virtual fabrication environment for semiconductor device structure development is discussed that enables the use of a selective epitaxy process to virtually model epitaxial growth of a crystalline material layer. The epitaxial growth occurs on a crystalline substrate surface of a virtually fabricated model device structure. A surface growth rate may be defined over possible 3D surface orientations of the virtually fabricated device structure by modeling the growth rates of the three major families of crystal planes. Growth rates along neighboring non-crystalline material may also be modeled.

Abstract: A 3-D multi-physics design environment (“3-D design environment”) for designing and simulating multi-physics devices such as MEMS devices is discussed. The 3-D design environment is programmatically integrated with a system modeling environment that is suitable for system-level design and simulation of analog-signal ICs, mixed-signal ICs and multi-physics systems. A parameterized MEMS device model is created in a 3-D graphical view in the 3-D design environment using parameterized model components that are each associated with an underlying behavioral model. After the MEMS device model is completed, it may be exported to a system modeling environment without subjecting the model to preliminary finite element meshing.

Abstract: A virtual fabrication environment for semiconductor device structure development is discussed. The insertion of a multi-etch process step using material-specific behavioral parameters into a process sequence enables a multi-physics, multi-material etching process to be simulated using a suitable numerical technique. The multi-etch process step accurately and realistically captures a wide range of etch behavior and geometry to provide in a virtual fabrication system a semi-physical approach to modeling multi-material etches based on a small set of input parameters that characterize the etch behavior.

Abstract: A virtual fabrication environment for semiconductor device structures that includes the use of virtual metrology measurement data to optimize a virtual fabrication sequence is described. Further, calibration of the virtual fabrication environment is performed by comparing virtual metrology data generated from a virtual fabrication run with a subset of measurements performed in a physical fabrication environment. Additionally, virtual experiments conducted in the virtual fabrication environment of the present invention generate multiple device structure models using ranges of process and design parameter variations for an integrated process flow and design space of interest.

Abstract: A virtual fabrication environment that enables 3D Design Rule Checks (DRCs) or Optical Rule Checks (ORCs) on 3D structural models of semiconductor devices to be performed is discussed. The virtual fabrication environment may perform 3D design rule checks, such as minimum line width, minimum space between features, and minimum contact area between adjacent materials, directly in 3D without making assumptions about the translation from 2D design data to a 3D structure effected by an integrated process flow for semiconductor devices. The required number of 3D design rule checks may therefore be significantly reduced from the number of design rule checks required in 2D environments. Embodiments may also perform the 3D design rule checks for a range of statistical variations in process and design parameters.

Abstract: A 3-D multi-physics design environment (“3-D design environment”) for designing and simulating multi-physics devices such as MEMS devices is discussed. The 3-D design environment is programmatically integrated with a system modeling environment that is suitable for system-level design and simulation of analog-signal ICs, mixed-signal ICs and multi-physics systems. A parameterized MEMS device model is created in a 3-D graphical view in the 3-D design environment using parameterized model components that are each associated with an underlying behavioral model. After the MEMS device model is completed, it may be exported to a system modeling environment without subjecting the model to preliminary finite element meshing.