Abstract: A direct memory access (DMA) engine schedules data transfer requests of a data processing system according to both an assigned transfer priority and the deadline for completing a transfer.

Abstract: A size and retry programmable multi-synchronous FIFO. In one embodiment, a multi-synchronous FIFO memory generally comprises a selectable number of addressable memory locations for storing information; read control means synchronized by a read clock for controlling pop transactions configured to read from one or more of the selected number of addressable memory locations; write control means synchronized by a write clock asynchronous to the read clock for controlling push transactions to write to one or more of the selected number of addressable memory locations; and selectable transaction retry control means configured to cause read control means to repeat selected pop transactions and/or cause write control means to repeat selected push transactions.

Abstract: A direct memory access (DMA) engine schedules data transfer requests of a data processing system according to both an assigned transfer priority and the deadline for completing a transfer.

Abstract: A direct memory access (DMA) engine schedules data transfer requests of a data processing system according to both an assigned transfer priority and the deadline for completing a transfer.

Abstract: A global timebase system and method for a system-on-chip synchronizes multiple clock domains in each of a plurality of receiver modules by broadcasting a global timebase count value as Gray code over a global timebase bus. A global timebase generator includes a binary counter and a binary-to-Gray-code converter. Each receiver module registers the global timebase count value with its own local clock and includes a Gray-code-to-binary converter. The converted value, in binary form, may be used as least significant bits of a globally synchronized local timebase. Most significant bits may be generated by a local binary counter incremented at each 1-to-0 transition of the most significant bit of the global timebase count value.

Abstract: A direct memory access (DMA) engine schedules data transfer requests of a system-on-chip data processing system according to both an assigned transfer priority and the deadline for completing a transfer. Transfer priority is based on a hardness representing the penalty for missing a deadline. Priorities are also assigned to zero-deadline transfer requests in which there is a penalty no matter how early the transfer completes. If desired, transfer requests may be scheduled in timeslices according to priority in order to bound the latency of lower priority requests, with the highest priority hard real-time transfers wherein the penalty for missing a deadline is severe are given the largest timeslice. Service requests for preparing a next data transfer are posted while a current transaction is in progress for maximum efficiency. Current transfers may be preempted whenever a higher urgency request is received.