Abstract: A method and a system are disclosed that enable an address at the edge router to be used to establish a multi-pipe virtual private network (MVPN) connecting controllers to multiple web enabled end user devices (EUDs) inside a security protected local area network (LAN). The EUDs connect to a central server (CS) outside the LAN during configuration establishing registration and identity (ID) for each EUD. Once the EUDs establish connection from inside the LAN, the CS is enabled to communicate with the EUDs using the address and ID provided during registration. The CS then acts as a facilitator establishing secure VPN connection between controllers in the cloud and the EUDs inside the LAN. CS further acts as a pass through for those LANs that do not allow direct connections to controllers outside the LAN. The CS continues to monitor the health of the overall system once connectivity is established.

Abstract: A method and a system are disclosed that enable an address at the edge router to be used to establish a multi-pipe virtual private network (MVPN) connecting controllers to multiple web enabled end user devices (EUDs) inside a security protected local area network (LAN). The EUDs connect to a central server (CS) outside the LAN during configuration establishing registration and identity (ID) for each EUD. Once the EUDs establish connection from inside the LAN, the CS is enabled to communicate with the EUDs using the address and ID provided during registration. The CS then acts as a facilitator establishing secure VPN connection between controllers in the cloud and the EUDs inside the LAN. CS further acts as a pass through for those LANs that do not allow direct connections to controllers outside the LAN. The CS continues to monitor the health of the overall system once connectivity is established.

Abstract: A method and a system are disclosed that enable an address at the edge router to be used to establish a multi-pipe virtual private network (MVPN) connecting controllers to multiple web enabled end user devices (EUDs) inside a security protected local area network (LAN). The EUDs connect to a central server (CS) outside the LAN during configuration establishing registration and identity (ID) for each EUD. Once the EUDs establish connection from inside the LAN, the CS is enabled to communicate with the EUDs using the address and ID provided during registration. The CS then acts as a facilitator establishing secure VPN connection between controllers in the cloud and the EUDs inside the LAN. CS further acts as a pass through for those LANs that do not allow direct connections to controllers outside the LAN. The CS continues to monitor the health of the overall system once connectivity is established.

Abstract: A multiply accumulate unit (“MAC”) that performs operations on packed integer data. In one embodiment, the MAC receives 2 32-bit data words which, depending on the specified mode of operation, each contain either four 8-bit operands, two 16-bit operands, or one 32-bit operand. Depending on the mode of operation, the MAC performs either sixteen 8×8 operations, four 16×16 operations, or one 32×32 operation. Results may be individually retrieved from registers and the corresponding accumulator cleared after the read cycle. In addition, the accumulators may be globally initialized. Two results from the 8×8 operations may be packed into a single 32-bit register. The MAC may also shift and saturate the products as required.

Abstract: A RISC processor using a fixed length standard instruction word (32-bit) consisting of a fixed-length (6-bit) operation code and two register fields, uses one of the register fields to give certain operation codes multiple meanings. For most operations, the register codes refer to general purpose registers as such. However, for certain operations, including move and add, register codes 30 and 31 in the source register code field of the instruction word indicate that the next instruction word contains immediate data for that operation instead of the operand being located in the specified register itself. Further, for load, store and jump operations, the source register codes 30 and 31 in the source register code field indicates that those registers are to be used as base or index registers for indexed addressing, with an offset in the following instruction word added to the general purpose register 30 or 31 contents to form the address.

Abstract: Configurable I/O circuitry having a plurality of configurable input/output elements, each of which connects one of a plurality of bits of a data bus to a corresponding one of the input/output terminals. Multiple clock selects and programmable enable signals can be connected to different interface elements to control activation of the interface element to which it is connected. The activated interface elements make up a virtual port that can be of any arbitrary bit width that is less than or equal to the fixed width of a physical port. This allows virtual ports on the data bus to be constructed that are narrower than the physical ports so that narrower data can be utilized in the port without causing the potential use of any of the data pins to be lost.

Abstract: Disclosed is a Multiply-Accumulate circuit that includes an exponent adder circuit, a mantissa multiplier circuit, a shifter, a full adder, and an accumulator. The product adder circuit receives two operands in a special combined data format which prescribes a mantissa and an exponent for both integer and floating point operands. The exponent adder circuit adds the exponents of the two operands. But if before the addition the exponent adder circuit detects an integer as an operand, it replaces the exponent of the integer by a substitute value in that addition. This substitute value is related to the number of bits of the mantissa of the integer. The mantissa multiplier circuit multiplies the two mantissas of the two operands. The shifter shifts the resultant product of multiplication into a pre-defined fixed point format according to the resultant sum of the addition generated by the exponent adder circuit. The full adder adds this shifted product to the current content of the accumulator.