Abstract: Systems and methods include translating a virtual memory address into a physical memory address in a multi-node system that is initiated by providing the virtual memory address at a source node. A determination is made that a translation for the virtual memory address does not exist. A physical node to query is determined based on the virtual memory address. An emulated remote translation table (ERTT) segment is queried on the determined physical node to see if the ERTT segment may provide a translation. If the translation is received then the translation may be loaded into a TLB on the source node. Otherwise a memory reference error may be generated for the entity or application referencing the invalid virtual memory address.

Abstract: Systems and methods for scheduling program units that are part of a process executed within an operating system are disclosed. Additionally, at least one thread is started within the operating system, the thread is associated with the process. Further, a plurality of streams within the thread are selected for execution on a multiple processor unit. Upon the occurrence of a context shifting event, one of the streams enters a kernel mode. If the first stream to enter kernel mode must block, then the execution of the other streams of the plurality of streams is also blocked.

Abstract: A system includes a memory, a plurality of pages held in the memory, an instruction translation look aside buffer (ITLB), a first data translation look aside buffer (DTLB), and a translation look aside (TLB) miss handler. The system also includes an executable/non-executable (x) indicator associated with each page in memory. The TLB miss handler sets the x-indicator for a particular page to indicate “non-executable” when that page is accessed in a mode that allows writing to that page. The ITLB or the ITLB miss handler refuses to allow instructions from a page with an associated x-indicator of “non-executable” to be loaded into the instruction buffer.