Abstract: The present invention provides an apparatus for monitoring access by a processor in a computing system to certain defined portions of memory. According to the present invention, the user specifies an address or range of address (the "watchword") in memory to be monitored. Each processor contains hardware which monitors outgoing memory references. If the processor attempts to access the defined portion of memory, the present invention generates a signal which is sent back to the issuing processor to inform it that referenced the watchword in memory. The present invention has several applications. In particular however, the present invention can be used in conjunction with debugging software packages as an aid for debugging user software programs on multiprocessing computer systems. Specifically, the present invention can be used to pinpoint which processor in a multiprocessing computer system accessed the watchword portion of memory.

Abstract: The present invention discloses an error recovery method for parallel architecture data storage devices. The present invention provides means for simultaneously arranging data on a plurality of recording surfaces so that intermittent and/or solid failures do not prevent access to the data stored thereon. A first error correcting code comprising a parity bit is generated for each dataword. The dataword and the parity bit are stored simultaneously and bit-wise to a plurality of recording surfaces. A second error correcting code is generated for a plurality of bits transmitted to a specific recording surface. The second error correcting code is written onto the same recording surface as the bits from which it was generated. The second error correcting code is used to detect and correct intermittent errors in the data read from a particular recording surface.