Abstract: A variable bit-length code processing circuit includes first, second and third registers (12, 20, 22) each of which is of 1 word, and memory data is loaded to the first register (12), and a variable bit-length code is withdrawn from the third register (22). The second register (20) and third register (22) are coupled to a barrel shifter (16) which barrel-shifts data of 2 words according to a barrel shift amount which is applied by a subtracter (30) on the basis of the number of the valid bits and the number of the remaining bits.
Type:
Grant
Filed:
June 20, 1996
Date of Patent:
September 29, 1998
Assignees:
Creative Design, Inc., Nintendo Co., Ltd.