Abstract: A circuit attenuates echo caused by line variations and a transformerless, high DC impedance, two-wire line interface. To reduce echo, a test tone is introduced on the communication line with all station units connected to the line. The resultant receive signal is conditioned through a peak detector, digitized and read by a processor. The resistive and capacitive characteristics of a network are iterated by the processor and the results remeasured. The network is set to the best combination for least echo by the processor. An interfacing system capacitively couples a plurality of sources to a two-wire communication pair by means of a plurality of differential voltage-to-current amplifiers. Each source uses a differential receiving amplifier to receive signals from the line and is resistively coupled in parallel to all the sourcing entities coupled to the communication line at that particular interface. There is an echo balance network associated with each source.

Abstract: A low power, low noise driving circuit for a bank of LEDs utilized in the station units of the MAN system is provided by coupling each bank of LEDs in a series circuit between the voltage supply and a constant current source. Each LED has a controllable logic switch in parallel across it and the switches are further in series circuit with each other to form a ladder network. Any selected LED may be turned off by closing its corresponding logic switch. The current continues to flow then through the shunting switch into the remaining LEDs in the series circuit that are on. A plurality of such ladder networks may be coupled in parallel with each other and each ladder network controlled by a switching gate which selectively couples it to the constant current source so that the LED ladder networks are operated at a predetermined duty cycle.

Abstract: Incremental values of a plurality of capacitors are programmably coupled through ROM core FETs with selective threshold voltages, EPROM core FETs, RAM cells, ROM fuse links or antifuse ROM links to a dummy bit line. The dummy bit line carries a bit line voltage to simulate either the worst case logical one or worst case logical zero within a read-only memory array of memory cells. The dummy bit line voltage is used as a control signal to a trigger circuit. The trigger circuit generates at the appropriate threshold a triggering signal used to control sense amplifiers coupled to the memory circuit. Therefore, by programmably altering the delay time on the dummy bit line, the read cycle of the memory can be programmably altered to either minimize the read time cycle to provide a fast, high quality memory product, or to maximize the read time cycle to provide for a slower but higher yield memory product at less expense.

Abstract: The invention is a telephone system capable of operating on a single internal telephone line as commonly found in the home or small businesses, which is economically implemented within an integrated circuit chip to provide a one chip telephone and which provides most of the components necessary for a full-featured, reliable and easy to install office communication system. The multiband audio network (MAN) transfers four audio bands and a digital data band over a single twisted pair of wire. A 6,000 bits per second full duplex digital data channel is also provided on the same twisted pair. Each station unit includes all the control and interface support necessary to perform conventional telephone functions. These functions include a combination of keyboard and display support circuitry such as strobe and debounce circuitry, LED buffers, piezo ring drivers, control registers and communication hardware.

Abstract: The invention is an improved bank select read only memory in which the bit lines and virtual ground lines are precharged to ground instead of being precharged to an internal low supply voltage. Both of the two virtual ground lines are selected for the selected bit and both selected virtual ground lines are driven to ground during the precharge phase. At the top of the memory array, all virtual ground lines in the memory array are precharged to ground during the precharge phase. Next, during the sensing phase, the operation of the two virtual ground lines for the selected bit is changed to selectively hold one virtual ground line at ground and switch the second virtual ground line to a positive voltage. All bit lines are precharged to ground during the precharge phase. In the following sensing phase, the selected bit line is driven positive by the selected memory core FET if it is programmed with a low threshold voltage.

Abstract: The address transition detection circuit is improved by holding the previously latched address signal until a predetermined delay after receipt of the new address signal.

Abstract: An improved precharge timing control is provided by turning off the first one of a series of precharge clocks PC0 by means of discharging a single dummy word line. The dummy word line is comprised of a plurality of dummy word line segments wherein each of the segments are charged in parallel, but discharged in series. The discharge time required of the plurality of word line segments is sufficient to allow discharge of an end of a selected word line in the read only memory to ground. Improved timing with good performance is achieved by turning off the earliest precharge clock PC0 among a series of precharge clocks PC0 and PC1, for example, so that an improved precharge time for the ROM core for a fast process parameter is realized.

Abstract: The performance of a very large scale integrated READ ONLY MEMORY circuit is improved by a number of different improvements in various circuits and methodologies utilized in the memory. One of the improvements relates to control of an output buffer by a control circuit. The output enable signal to the output buffer is selectively inhibited by the control circuit which determines when the memory cycle is actually completed. Only after the memory cycle is actually completed is the conventional chip enable signal, CE, coupled to the enable input in the output buffer.

Abstract: The invention is a control circuit for controlling an interrupt driver coupled to the data outputs of a memory having address transition detection circuitry. The memory is operable in a standby and an active memory mode in sequential memory cycles. The control circuit comprises an output enable latch circuit which provides internal memory signal of whether the memory was operating in the standby or active mode during a previous memory cycle and a data latch circuit which provides an internal memory signal of whether a new read cycle is beginning within the memory. The data latch circuit is reset when address detection has occurred within the memory. A logic circuit combines an output of the data latch circuit, which is indicative of a memory read cycle, with an output of the output enable latch circuit, which is indicative of whether the prior memory cycle was standby or active.

Abstract: Operation of an address latch circuit in a memory is conditioned on first receiving a ground surge control logic signal, SURG, which is generated only when data output drivers switch. This prevents noise from these same drivers from falsely addressing the memory. Metastability is prevented by selecting the trigger points of the gates which make up the latch such that an output is not generated until input or intermediate circuitry has stabilized and by providing a favored output condition in the input or intermediate circuitry when conflict between almost simultaneous inputs occur. Feedback of the output of the latch to its input further reduces metastability.

Abstract: A circuit which differentially amplifies voltages that are close to ground with differences of about 0.15 volts uses voltage level shifters, a cross coupled current source and inverters to provide increased speed, accuracy, and gain. Symmetric cross coupled current sources are used in a differential amplifier to provide the differential amplifier with a balanced load. A symmetric and balanced layout senses smaller voltage differences and operates faster than would otherwise be possible. The gain of the cross coupled current source is controlled by four FETs. Voltage level shifters at the input to the differential amplifier allow the differential amplifier to sense signals that are close to ground with a voltage difference of about 0.15 volts. The voltage level shifters also shift the signals to a voltage that increases the gain of the differential amplifier. Two inverters block half level signals from being outputted until the sense amplifier data has been latched.

Abstract: The performance of a very large scale integrated READ ONLY MEMORY circuit is improved by improvements in various circuits and methodologies utilized in the memory. Appropriate bias levels are generated by a bias circuit for use in the output buffer according to whether a process temperature and voltage variations within the memory circuit are such that variation sensitive components will be slowed upon the occurrence of such variations. The bias circuit otherwise generates a bias signal appropriate for fast speed operations within the output buffer circuit when process temperature and voltage variations are such that they do not effect circuit speed of sensitive circuit portions. The back bias generator which operates asynchronously from the memory cycle is improved by disabling the charge pumping action during a memory cycle.

Abstract: A telephone communication system for communicating between a plurality of exterior telephone lines and a single common in-house two wire line is comprised of a control unit for coupling to the plurality of exterior telephone lines and for controlling communication between the plurality of telephone lines and the common two wire line. A plurality of station units are coupled remotely throughout the building to the common two wire line. The control unit communicates on the digital channel with the plurality of station units in a time frame subdivided into a plurality of time slots. A specified portion of each time slot is reserved for control communication between the control unit and each one of the plurality of station units. A synchronization signal is transmitted for phase locking all the station units to the control unit clock and a common frame synchronization signal is used to align all units in time.

Abstract: The invention is a dynamic ROM design for read cycle interrupts. The clock scheme of the improved memory generates a primary start clock. The relatively long pulse time of START when high is provided for setting the latches. This pulse duration is controlled by PCOK or OWDN one shot circuit.When an address interrupt occurs early in the read cycle, while PCOK or OWDN clock is low, and START is high, these one shot circuits provide a simple means of restarting the cycle by continuing the precharge phase of the cycle with no effect on most of the secondary clocks in the memory. Only those clocks relating to the new address inputs are effected by the early interrupt. This results in less power dissipation and less bus noise.

Abstract: The invention is an improved bank select read only memory in which the bit lines and virtual ground lines are all precharged to ground instead of being precharged to an internal low supply voltage. Both of the two virtual ground lines are selected for the selected bit and both selected virtual ground lines are driven to ground during the precharge phase. At the top of the memory array, all virtual ground lines in the memory array are precharged to ground during the precharge phase.Next during the sensing phase, the operation of the two virtual ground lines for the selected bit is changed to selectively hold one virtual ground line at ground and switch the second virtual ground line to a positive voltage. All bit lines are precharged to ground during the precharge phase.In the following sensing phase, the selected bit line is driven positive by the selected memory core FET if it is programmed with a low threshold voltage.

Abstract: In a read-only memory core improved generation of a trigger signal, TRIG, is achieved through the use of a pair of cascaded CMOS differential amplifiers which are directly interconnected and directly coupled to a CMOS inverter from which the trigger signal, TRIG, is derived. The cascaded differential amplifiers have trigger points set by varying the channel widths of the input FETs to the CMOS differential amplifiers, or by adjusting the gains of the CMOS differential amplifiers to match the trigger point of the CMOS inverter coupled to its output. The trigger circuit is powered down to zero power dissipation whenever it is inactive.

Abstract: The operation of the sense amplifier in a VLSI memory is improved by providing dummy bit lines corresponding to the ON state and OFF state of the memory cells, averaging the voltage on the dummy bit lines, and comparing that average to the bit line voltage to generate a differential sense output. Leakage currents and voltages common to both the dummy bit lines and selected bit line are thus cancelled out.Sense amplifiers incorporating this advantage may also be used in combination with a dynamic latch which is selectively disconnected from the memory array at all times other than during a memory cycle to avoid noise interference.Dummy word lines used in combination with dummy predecoder and decoder are used to make on-chip determinations of the transition points when an address signal is valid and complete. The actual initiation of the addressing of the memory may then be triggered according to a modeled transition point within each memory circuit.

Abstract: The performance of a Very Large Scale Integrated Read-Only Memory Circuit is improved by providing an architecture for columns of memory cells so that a signal from an addressed memory cell need propagate on diffusion bit lines by a distance approximately equal to the length of the diffusion bit line within a single block of memory cells. The architecture of the memory layout is improved by providing bit line and virtual ground line contacts at opposing ends of the memory block and by replicating the memory block through mirror symmetry on the semiconductor substrate. The memory array is further improved by providing bank selection transistors for each bank at each opposing end of a memory block so the propagation signal of an addressed memory cell need only travel the length of a single bit diffusion line in the bank.