Abstract: An integrated circuit testing device, such as an ATE, configured with an architecture comprising a distinct software layer and a distinct hardware layer with an interface for tester abstraction providing a communication conduit between the software layer and the hardware layer. The software layer communicates in device under test terms whereas the hardware layer communicates in the terms of the testing apparatus. Various communication interface points are provided to the software and hardware layers, as well as the interface for tester abstraction.
Abstract: The present invention relates to test systems for testing integrated circuit devices and to calibration associated systems and methods. One embodiment of the invention provides a test system formatter including: a plurality of event logic interfaces, each event logic interface capable of receiving and decoding timing signals; a plurality of delay line elements (DLEs), each DLE being coupled to a corresponding event logic interface and being capable of generating timing markers corresponding to signals received from the corresponding event logic interface; drive logic coupled to the plurality of DLEs, having first and second outputs and operative to produce first and second formatted levels on the first and second outputs in response to timing markers received from the plurality of DLEs; response logic coupled to the plurality of DLEs, having first and second inputs and operative to produce strobe markers in response to timing markers received from the plurality of DLEs; and a loop-back circuit.