Abstract: A decision-feedback equalizer (DFE) can be operated at higher frequencies when parallelization and pre-computation techniques are employed. Disclosed herein is a DFE design suitable for equalizing receive signals with bit rates above 10 GHz, making it feasible to employ decision feedback equalization in silicon-based optical transceiver modules.

Abstract: A decision-feedback equalizer (DFE) can be operated at higher frequencies when parallelization and pre-computation techniques are employed. Disclosed herein is a DFE design suitable for equalizing receive signals with bit rates above 10 GHz, making it feasible to employ decision feedback equalization in silicon-based optical transceiver modules.

Abstract: A parallel implementation of the Viterbi decoder becomes more efficient when it employs end-state information passing as disclosed herein. The improved efficiency enables the usage of less area and/or provides the capacity to handle higher data rates within a given heat budget. In at least some embodiments, a decoder chip employs multiple decoders that operate in parallel on a stream of overlapping data blocks, using add-compare-select operations, to obtain a sequence of state metrics representing a most likely path to each state. Each decoder passes information indicative of a selected end-state for a decoder operating on a preceding data block. Each decoder in turn receives, from a decoder operating on a subsequent data block, the information indicative of the selected end-state. The end-state information eliminates any need for post-data processing, thereby abbreviating the decoding process.

Abstract: Disclosed is at least one flash analog-to-digital converter embodiment having a linear voltage ladder, a set of comparators each of which is coupled to one or more operational amplifiers by a sampling switch. Each of the sampling switches samples the comparator output, using the parasitic capacitance of the operational amplifier to hold the voltage. The sampling switches may be single transistors. Some embodiments further include, for each comparator, multiple operational amplifiers each of which drives a binary latch via a gating switch. The gating switches operate in sequence to distribute sequential samples to different latches. At least some embodiments of the flash converter further include an automatic gain control (AGC) that has both differential input terminals and differential output terminals. In such embodiments the comparators compare the differential output of the AGC to a differential reference voltage, and may further provide the result as a differential signal.

Abstract: A decision-feedback equalizer (DFE) can be operated at higher frequencies when parallelization and pre-computation techniques are employed. Disclosed herein is a DFE design that operates at frequencies above 10 GHz, making it feasible to employ decision feedback equalization in optical transceiver modules. An adaptation technique is also disclosed to maximize communications reliability. The adaptation module can be treated as a straightforward extension of the pre-computation unit. At least some method embodiments include, in each time interval: sampling a signal that is partially compensated by a feedback signal; comparing the sampled signal to a set of thresholds to determine multiple speculative decisions; selecting and outputting one of the speculative decisions based on preceding decisions; and updating a counter if the sampled signal falls within a window proximate to a given threshold. Once a predetermined interval has elapsed, the value accumulated by the counter is used to adjust the given threshold.

Abstract: Disclosed is at least one flash analog-to-digital converter embodiment having a linear voltage ladder, a set of comparators each of which is coupled to one or more operational amplifiers by a sampling switch. Each of the sampling switches samples the comparator output, using the parasitic capacitance of the operational amplifier to hold the voltage. The sampling switches may be single transistors. Some embodiments further include, for each comparator, multiple operational amplifiers each of which drives a binary latch via a gating switch. The gating switches operate in sequence to distribute sequential samples to different latches. At least some embodiments of the flash converter further include an automatic gain control (AGC) that has both differential input terminals and differential output terminals. In such embodiments the comparators compare the differential output of the AGC to a differential reference voltage, and may further provide the result as a differential signal.

Abstract: A decision-feedback equalizer (DFE) can be operated at higher frequencies when parallelization and pre-computation techniques are employed. Disclosed herein is a DFE design that operates at frequencies above 10 GHz, making it feasible to employ decision feedback equalization in optical transceiver modules. An adaptation technique is also disclosed to maximize communications reliability. The adaptation module can be treated as a straightforward extension of the pre-computation unit. At least some method embodiments include, in each time interval: sampling a signal that is partially compensated by a feedback signal; comparing the sampled signal to a set of thresholds to determine multiple speculative decisions; selecting and outputting one of the speculative decisions based on preceding decisions; and updating a counter if the sampled signal falls within a window proximate to a given threshold. Once a predetermined interval has elapsed, the value accumulated by the counter is used to adjust the given threshold.

Abstract: A parallel implementation of the Viterbi decoder becomes more efficient when it employs end-state information passing as disclosed herein. The improved efficiency enables the usage of less area and/or provides the capacity to handle higher data rates within a given heat budget. In at least some embodiments, a decoder chip employs multiple decoders that operate in parallel on a stream of overlapping data blocks, using add-compare-select operations, to obtain a sequence of state metrics representing a most likely path to each state. Each decoder passes information indicative of a selected end-state for a decoder operating on a preceding data block. Each decoder in turn receives, from a decoder operating on a subsequent data block, the information indicative of the selected end-state. The end-state information eliminates any need for post-data processing, thereby abbreviating the decoding process.