Abstract: An RF power device comprising a power transistor fabricated in a first semiconductor chip and a MOSCAP type structure fabricated in a second semiconductor chip. A voltage limiting device is provided for protecting the power transistor from input voltage spikes and is preferably fabricated in the semiconductor chip along with the MOSCAP. Alternatively, the voltage limiting device can be a discrete element fabricated on or adjacent to the capacitor semiconductor chip. By removing the voltage limiting device from the power transistor chip, fabrication and testing of the voltage limiting device is enhanced, and semiconductor area for the power device is increased and aids in flexibility of device fabrication.

Abstract: A coplanar coupler for use with microstrip input and output ports includes a printed circuit substrate in which first and second metal input ports are formed on a top surface and cooperate with a metal layer on the bottom surface as microstrip lines, and first and second metal output ports formed on the top surface which cooperate with the metal layer on the bottom surface as microstrip lines. The metal layer on the bottom surface functions as a ground plane for the input ports and the output ports, the metal layer being removed in a coupler region underlying at least portions of the metal input and output ports and extending therebetween. First and second metal lines are formed on the bottom surface in the coupler region and function as a coplanar coupler for the input and output ports. Electrical vias in the substrate interconnect the ports and the coplanar coupler.

Abstract: An inexpensive method of providing uniform and consistent spacing between a semiconductor die and a supporting substrate includes providing relatively rigid spacers such as a plurality of lengths of wires or a plurality of bumps on the mounting surface for the chip. The spacers allow a uniform desired spacing of the die from the supporting substrate when attached by an epoxy.

Abstract: Methods of fabricating a high power RF lateral diffused MOS transistor (LDMOS) having increased reliability includes fabricating an N-drift region for the drain prior to fabrication of the gate contact and other process steps in fabricating the transistor. The resulting device has reduced adverse affects from hot carrier injection including reduced threshold voltage shift over time and reduced maximum current reduction over time. Linearity of device is maximized along with increased reliability while channel length is reduced.

Abstract: The breakdown voltage of a semiconductor device, such as a transistor fabricated in a device region in and abutting the surface of a semiconductor body with a field oxide surrounding the device region, is improved by etching the field oxide abutting the device region to reduce the thickness thereof to about 0.6-1.4 &mgr;m and then forming a field plate in the recessed field oxide which is capacitively coupled to the underlying semiconductor body. The field plate can be floating, connected to a voltage potential, or connected to the semiconductor device.