Patents Assigned to Crest Semiconductors, Inc.
  • Patent number: 9071270
    Abstract: A time-interleaved Analog-to-Digital Converter (ADC) includes a set of time multiplexed sub-ADC circuits, each sub-ADC circuit comprising a sample-and-hold circuit. Each sample-and-hold circuit includes a bootstrap circuit for maintaining a constant voltage level between an input terminal of a switch and a gate terminal of the switch, the switch for switching between a track mode and a hold mode, and a capacitor bank associated with the bootstrap circuit such that a setting of the capacitor bank affects the voltage level.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: June 30, 2015
    Assignee: CREST SEMICONDUCTORS, INC.
    Inventors: Tracy Johancsik, Ryan James Kier, Yusuf Haque
  • Patent number: 8890739
    Abstract: A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a clock signal for each of the ADCs such that edges of said clock signals trigger sampling of an input signal by the ADCs; and a timing adjustment circuit to receive and adjust the clock signals before the clock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and circuit for adjusting the bandwidth of the plurality of ADCs.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: November 18, 2014
    Assignee: Crest Semiconductors, Inc.
    Inventors: Donald E. Lewis, Ryan James Kier, Rex K. Hales, Yusuf Haque
  • Patent number: 8890729
    Abstract: A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a dock signal for each of the plurality of ADCs such that edges of said clock signals trigger sampling of an input signal by the plurality of ADCs; and a timing adjustment circuit to receive and adjust the dock signals before the dock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and a random number generator to pseudo randomly select which ADC samples the input signal; and a circuit for adjusting the bandwidth of the plurality of ADCs.
    Type: Grant
    Filed: January 26, 2013
    Date of Patent: November 18, 2014
    Assignee: Crest Semiconductors, Inc.
    Inventors: Donald E. Lewis, Ryan James Kier, Rex K. Hales, Yusuf A. Haque
  • Publication number: 20140152478
    Abstract: A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a dock signal for each of the plurality of ADCs such that edges of said clock signals trigger sampling of an input signal by the plurality of ADCs; and a timing adjustment circuit to receive and adjust the dock signals before the dock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and a random number generator to pseudo randomly select which ADC samples the input signal; and a circuit for adjusting the bandwidth of the plurality of ADCs.
    Type: Application
    Filed: January 26, 2013
    Publication date: June 5, 2014
    Applicant: CREST SEMICONDUCTORS, INC.
    Inventors: Donald E. Lewis, Ryan James Kier, Rex K. Hales, Yusuf A. Haque
  • Publication number: 20140152477
    Abstract: A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a clock signal for each of the ADCs such that edges of said clock signals trigger sampling of an input signal by the ADCs; and a timing adjustment circuit to receive and adjust the clock signals before the clock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and circuit for adjusting the bandwidth of the plurality of ADCs.
    Type: Application
    Filed: December 5, 2012
    Publication date: June 5, 2014
    Applicant: CREST SEMICONDUCTORS, INC.
    Inventors: Donald E. Lewis, Ryan James Kier, Rex K. Hales, Yusuf Haque
  • Patent number: 8542143
    Abstract: A pipelined Analog-to-Digital Converter (ADC) stage includes a main sampling path having a first filter in series with a first sample and hold circuit and a sub-ADC sampling path having a second filter in series with a second sample and hold circuit driving a sub-ADC connected to a sub-Digital-to-Analog Converter (DAC). The frequency response of the main sampling path is matched to a frequency response of the sub-ADC sampling path such that a residue signal of the pipelined ADC stage stays within range.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: September 24, 2013
    Assignee: Crest Semiconductors, Inc.
    Inventors: Yusuf Haque, Ryan James Kier, Rex K. Hales, Paul Talmage Watkins, Marcellus C. Harper
  • Publication number: 20130234870
    Abstract: A pipelined Analog-to-Digital Converter (ADC) stage includes a main sampling path having a first filter in series with a first sample and hold circuit and a sub-ADC sampling path having a second filter in series with a second sample and hold circuit driving a sub-ADC connected to a sub-Digital-to-Analog Converter (DAC). The frequency response of the main sampling path is matched to a frequency response of the sub-ADC sampling path such that a residue signal of the pipelined ADC stage stays within range.
    Type: Application
    Filed: March 6, 2012
    Publication date: September 12, 2013
    Applicant: CREST SEMICONDUCTORS, INC
    Inventors: Yusuf Haque, Ryan James Kier, Rex K. Hales, Paul Talmage Watkins, Marcellus C. Harper
  • Patent number: 8525596
    Abstract: A reference buffer amplifier within an integrated circuit includes a first output terminal connected to a first bond pad, the first bond pad being connected to a first external pin of the integrated circuit chip, the first external pin to allow an external capacitance to be connected to the output terminal. The reference buffer further includes a variable, settable resistance sub-circuit connected to a second bond pad, the second bond pad also being connected to the first external pin. The resistance sub-circuit is configured to be set to exhibit a resistance value to critically dampen a response of the reference buffer amplifier.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: September 3, 2013
    Assignee: Crest Semiconductors, Inc.
    Inventors: Tracy Johancsik, Rex K. Hales, Ryan James Kier, Yusuf Haque
  • Patent number: 8525556
    Abstract: A time-interleaved sample-and-hold system includes a first sample-and-hold circuit and a second sample-and-hold circuit. The first sample-and-hold circuit and the second sample-and-hold circuit share a common sampling switch. A method of remediating a timing offset between a first sample-and-hold circuit and a second sample-and-hold circuit in a time-interleaved sample-and-hold system includes switching at least one shunt capacitor disposed between two logic gates in a timing circuit to adjust a delay between a timing signal for a common sampling switch electrically coupled to the first and second sample-and-hold circuits and a timing signal for at least one of the sample-and-hold circuits.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: September 3, 2013
    Assignee: Crest Semiconductors, Inc.
    Inventors: Ramesh Kumar Singh, Yusuf Haque, Donald E. Lewis
  • Patent number: 8497790
    Abstract: A pipelined Analog-to-Digital Converter (ADC) includes circuitry to characterize capacitors associated with a Multiplying-Digital-to-Analog Converter (MDAC) of a stage of said pipelined ADC, said capacitors contributing to a gain of said pipelined ADC, circuitry to connect a subset of said capacitors not currently being characterized to reference signals of said pipelined ADC such that a residue signal of said stage stays within an input range of an instrument measuring said residue signal, circuitry to calculate said gain of said pipelined ADC using said capacitor characterizations, and an output adjusting component to digitally change an output of said pipelined ADC to compensate for said calculated gain.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: July 30, 2013
    Assignee: Crest Semiconductors, Inc.
    Inventors: Donald E. Lewis, Ryan James Kier, Paul Talmage Watkins, Rex K. Hales, Yusuf Haque
  • Patent number: 8466818
    Abstract: A time-interleaved Analog-to-Digital Converter (ADC) includes a set of sub-ADC circuits. Each sub-ADC circuit comprises a sample-and-hold circuit. Each sample-and-hold circuit includes a bootstrap circuit for maintaining a constant voltage level between an input terminal of a switch and a gate terminal of the switch, the switch for switching between a sample mode and a hold mode. Each sample and hold circuit also includes a capacitor bank associated with the bootstrap circuit such that a setting of the capacitor bank affects an ON state intrinsic resistance of the switch by affecting the voltage level.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: June 18, 2013
    Assignee: Crest Semiconductors, Inc.
    Inventors: Tracy Johancsik, Ryan James Kier, Yusuf Haque
  • Publication number: 20130141261
    Abstract: A time-interleaved Analog-to-Digital Converter (ADC) includes a set of sub-ADC circuits. Each sub-ADC circuit comprises a sample-and-hold circuit. Each sample-and-hold circuit includes a bootstrap circuit for maintaining a constant voltage level between an input terminal of a switch and a gate terminal of the switch, the switch for switching between a sample mode and a hold mode. Each sample and hold circuit also includes a capacitor bank associated with the bootstrap circuit such that a setting of the capacitor bank affects an ON state intrinsic resistance of the switch by affecting the voltage level.
    Type: Application
    Filed: December 1, 2011
    Publication date: June 6, 2013
    Applicant: CREST SEMICONDUCTORS, INC
    Inventors: Tracy Johancsik, Ryan James Kier, Yusuf Haque
  • Publication number: 20130120066
    Abstract: A reference buffer amplifier within an integrated circuit includes a first output terminal connected to a first bond pad, the first bond pad being connected to a first external pin of the integrated circuit chip, the first external pin to allow an external capacitance to be connected to the output terminal. The reference buffer further includes a variable, settable resistance sub-circuit connected to a second bond pad, the second bond pad also being connected to the first external pin. The resistance sub-circuit is configured to be set to exhibit a resistance value to critically dampen a response of the reference buffer amplifier.
    Type: Application
    Filed: November 11, 2011
    Publication date: May 16, 2013
    Applicant: CREST SEMICONDUCTORS, INC
    Inventors: Tracy Johancsik, Rex K. Hales, Ryan James Kier, Yusuf Haque
  • Patent number: 8410968
    Abstract: A track and hold circuit includes an input, a first output configured to produce a first output signal, and a second output configured to produce a second output signal while the track and hold circuit is in a first mode. While the track and hold circuit is in a second mode, the second output signal is combined with the first output signal and output on the first output.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: April 2, 2013
    Assignee: Crest Semiconductors, Inc.
    Inventor: Tracy Johancsik
  • Patent number: 8410967
    Abstract: An analog-to-digital converter includes a comparator configured to receive a first input signal and a second input signal, in which at least one of the input signals is received between two transistors, each of the transistors being in common-gate configuration. A method for comparing input signals performed by a comparator circuit includes: receiving a first input signal between a drain terminal of a first transistor of the comparator circuit and a source terminal of a second transistor of the comparator circuit; receiving a second input signal; and outputting a value based on a comparison of the first input signal and the second input signal.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: April 2, 2013
    Assignee: Crest Semiconductors, Inc.
    Inventors: Rex K. Hales, Paul Talmage Watkins
  • Patent number: 8344922
    Abstract: A Digital-to-Analog Converter (DAC) with code independent output capacitance includes circuitry configured to convert a digital input signal to an analog output signal in a manner such that at least one output terminal of the DAC exhibits a constant capacitance value for up to all received values of the digital input signal. A method for converting a digital signal to an analog signal with a DAC includes converting a digital input signal to an analog output signal in a manner such that at least one output terminal of the DAC exhibits a constant capacitance value for up to all received values of the digital input signal.
    Type: Grant
    Filed: August 3, 2010
    Date of Patent: January 1, 2013
    Assignee: Crest Semiconductors, Inc.
    Inventors: Ryan James Kier, Paul Talmage Watkins, Yusuf Aminul Haque
  • Patent number: 8344722
    Abstract: A method for measuring electric current applied to a load includes: with a sensor element having an inaccuracy, measuring an electric current supplied to a load to produce a measurement of the electric current; with the sensor element, measuring the electric current with an added perturbation current; and using measurements of the electric current taken with and without the perturbation current to refine the measurement of the electric current.
    Type: Grant
    Filed: May 17, 2010
    Date of Patent: January 1, 2013
    Assignee: Crest Semiconductors, Inc.
    Inventors: Marcellus C. Harper, William Picken, Yusuf Haque
  • Patent number: 8242946
    Abstract: A pipelined Analog-to-Digital Converter (ADC) comprising a number of stages, at least one of the stages includes a sample and hold circuit. The sample and hold circuit includes a first output connected to an input of a sub-ADC, an output of the sub-ADC connected to an input of a Digital-to-Analog Converter (DAC), an output of the DAC connected to a node, and a second output connected to the node. The sample and hold circuit is configured to independently scale a signal produced by the first output and a signal produced by the second output.
    Type: Grant
    Filed: August 3, 2010
    Date of Patent: August 14, 2012
    Assignee: Crest Semiconductors, Inc.
    Inventors: Tracy Johancsik, Rex K. Hales