Abstract: A method of forming a non-volatile memory device includes providing a substrate having a surface, depositing a dielectric overlying the surface, forming a first wiring structure overlying the dielectric, depositing silicon material overlying the first wiring structure, the silicon layer having a thickness of less than about 100 Angstroms, depositing silicon germanium material at a temperature raging from about 400 to about 490 Degrees Celsius overlying the first wiring structure using the silicon layer as a seed layer, wherein the silicon germanium material is substantially free of voids and has polycrystalline characteristics, depositing resistive switching material (e.g. amorphous silicon material) overlying the silicon germanium material, depositing a conductive material overlying the resistive material, and forming a second wiring structure overlying the conductive material.

Abstract: Providing for preconditioning of multi-programmable, two-terminal memory for improved endurance and switching functionality is described herein. By way of example, one or more pre-conditioning signals can be applied to a memory cell post-fabrication. The preconditioning signal(s) can have relatively small power, avoiding programming of the memory cell, compared with an associated program signal. The preconditioning signal(s) can facilitate reliable erasure of the memory cell following subsequent programming at normal programming power. Accordingly, switching functionality of the two-terminal memory can be preserved, maintaining the multi-programmable nature of the memory cell.

Abstract: Provision of fabrication, construction, and/or assembly of a two-terminal memory device is described herein. The two-terminal memory device can include an active region with a silicon bearing layer, an interface layer, and an active metal layer. The interface layer can be grown on the silicon bearing layer, and the growth of the interface layer can be regulated with N2O plasma.

Abstract: Providing for two-terminal memory having an inherent rectifying characteristic(s) is described herein. By way of example, the two-terminal memory can be a resistive switching device having one or more “on” states and an “off” state, to facilitate storage of digital information. A conductive filament can be electrically isolated from an electrode of the two-terminal memory by a thin tunneling layer, which permits a tunneling current for voltages greater in magnitude than a positive rectifying voltage or a negative rectifying voltage. The two-terminal memory cell can therefore have high resistance to small voltages, mitigating leakage currents in an array of the two-terminal memory cells. In addition, the memory cell can be conductive above a rectifying voltage, enabling reading of the memory cell in response to a suitable read bias, and erasing of the memory cell in response to a suitable negative erase bias.

Abstract: Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections of the signal input lines and signal output lines. The RRAM memory cell can include a voltage divider comprising multiple programmable resistive elements arranged electrically in series across a VCC and VSS of the FPGA. A common node of the voltage divider drives a gate of a pass gate transistor configured to activate or deactivate the intersection. The disclosed RRAM memory can provide high transistor density, high logic utilization, fast programming speed, radiation immunity, fast power up and significant benefits for FPGA technology.

Abstract: A method for programming a non-memory device comprising a plurality of resistive switching device. Each of the plurality of resistive switching device includes a resistive switching material characterized by a resistance characterized by a state depending on a conductive filament structure. A first programming code file to configure a system to perform a predetermined task is provided. The programmability of each of the plurality of resistive switching device is maintained. The system receives the first programming code file, executing the first programming code file, and verifies and validates that the system performs the predetermined task. Once the first programming code file is validated, the conductive filament in one or more resistive switching device is fixed spatially in a portion of the resistive switching material of the respective one or more resistive switching device by applying joule heating programming. The programmability of each of the memory device is removed.

Abstract: Provision of fabrication, construction, and/or assembly of a two-terminal memory device is described herein. The two-terminal memory device can include an active region with a silicon bearing layer, an interface layer, and an active metal layer. The interface layer can created comprising a non-stoichimetric sub-oxide that can be a combination of multiple silicon and/or silicon oxide layers with an aggregate chemical formula of SiOX, where X can be a non-integer greater than zero and less than 2. The sub-oxide can be created in a variety of ways, including various techniques related to growing the sub-oxide, depositing the sub-oxide, or transforming an extant film into the sub-oxide.

Abstract: A solid state memory comprises a top electrode, a bottom electrode and an insulating switching medium that is disposed at a thickness based on a predetermined function. The insulating switching medium generates a conduction path in response to an electric signal applied to the device. The thickness of the insulating switching medium is a function of a filament width of the conduction path and operates to prevent rupture of a semi-stable region. The semi-stable region maintains filament structure over time and does not degrade into retention failure. The solid state memory can comprise one or more conducting layers that can operate to control the conductance at an on-state of the memory and offer oxygen vacancies or metal ions to the switching medium. The function of the thickness of the insulating switching medium can vary depending upon the number of conduction layers disposed at the insulating switching medium.

Abstract: A non-volatile memory device structure comprises a substrate having a surface region and a first dielectric material overlying the surface region. The device structure includes a state change device overlying the first dielectric material, the state change device comprising a first wiring structure configured to spatially extend in a first direction, a switching element comprising a first amorphous silicon material overlying the first wiring structure, and a second wiring structure configured to spatially extend in a second direction perpendicular to the first direction. The device structure includes a first thin film transistor device configured to cause the state change device to change from a first state to a second state. The thin film transistor device comprises a first active region, a second active region, a gate structure overlying a gate dielectric layer, and a channel region. The first active region is in electrical contact with the second wiring structure.

Abstract: A non-volatile resistive switching memory device. The device includes a first electrode, a second electrode, a switching material in direct contact with a metal region of the second electrode, and a resistive material disposed between the second electrode and the switching material. The resistive material has an ohmic characteristic and a resistance substantially the same as an on state resistance of the switching device. The resistive material allows for a change in a resistance of the switching material upon application of voltage pulse without time delay and free of a reverse bias after the voltage pulse. The first voltage pulse causes a programming current to flow from the second electrode to the first electrode. The resistive material further causes the programming current to be no greater than a predetermined value.

Abstract: Providing for a high performance and efficiency NAND architecture is described herein. By way of example, a NAND array is disclosed comprising memory cells having a 1 transistor-1 two-terminal memory device (IT-1D) arrangement. Memory cells of the NAND array can be arranged electrically in serial with respect to each other, from source to drain. Moreover, respective memory cells comprise a transistor component connected in parallel to a two-terminal memory device. In some embodiments, a resistance of the activated transistor component is selected to be substantially less than that of the two-terminal memory device, and the resistance of the deactivated transistor component is selected to be substantially higher than the two-terminal memory device. Accordingly, by activating or deactivating the transistor component, a signal applied to the memory cell can be shorted past the two-terminal memory device, or directed through the two-terminal memory device, respectively.

Abstract: A two-terminal memory cell comprises a dual mode of operation in a unipolar mode and bipolar mode for a programming or On-state and for an erase or Off-state of the cell. The two-terminal memory cell is field programmable and can be flexibly designed or integrated into existing architecture. The two-terminal memory comprises a first electrode layer and a second electrode layer with a switching layer disposed between that has an electrical insulator material. A semiconductor layer is disposed between the switching layer and at least one of the first electrode or the second electrode. The switching layer generates a conductive path that is configured to be in a program state and an erase state, based on a bipolar mode and a unipolar mode.

Abstract: Providing for rectified-switching of a two-terminal solid state memory cell is described herein. By way of example, the subject disclosure provides a solid state device exhibiting rectified resistive switching characteristics that can be fabricated with semiconductor fabrication techniques. The solid state device can comprise a metal ion layer adjacent to an electrically resistive diffusion layer, which is at least in part permeable to conductive ions of the metal ion layer. A pair of electrodes can be placed, respectively, on opposite sides of the adjacent ion layer and electrically resistive diffusion layer to facilitate operating on the two-terminal solid state memory cell. In operation, a program voltage induces conductive ions to form a semi-stable conductive filament within the diffusion layer, which partially deforms in response to reduction in the program voltage.

Abstract: Provision of fabrication, construction, and/or assembly of a memory device including a two-terminal memory portion is described herein. The two-terminal memory device fabrication can provide enhanced capabilities in connection with precisely tuning on-state current over a greater possible range.

Abstract: A non-volatile memory device structure. The device structure includes a first electrode, a second electrode and a state change material sandwiched between the first electrode and the second electrode. In a specific embodiment, the first electrode includes a p+ type polycrystalline silicon material or a p+ type silicon germanium material. The state change material includes an n? type zinc oxide material. The second electrode includes a doped zinc oxide material. The doped zinc oxide material can be B2O3:ZnO, In2O3:ZnO, Al2O3:ZnO or Ga2O3:ZnO. The n? type zinc oxide material and the p+ type silicon material (or p+ polycrystalline silicon germanium material) further form a diode device or steering device for the non-volatile memory device.

Abstract: A memory system includes a memory device. The memory device includes a substrate. A memory array defines a plurality of pages, each page including a data area for storing data and a spare area for storing a program/erase (PE) count value, the PE count value indicating a number of PE cycles performed on the page. A PE count circuit is configured to perform a PE count read operation on a target page. A host determines whether to perform a data write operation on the target page or another PE count read operation on a new target page based on a result of the PE count read operation. PE cycles of a page are controlled by the PE count read operation. The memory array and the PE count circuit are formed in different layers of the substrate.

Abstract: A method of forming a non-volatile memory device, includes providing a substrate, forming a first dielectric over the substrate, forming a first wiring structure over the first dielectric, forming a first conductor in contact with the first wiring structure, forming a polycrystalline p+ SiGe material over the first conductor at a deposition temperature ranging from about 350 to about 500 Degrees Celsius, forming a polycrystalline silicon conformally over the SiGe material using the SiGe material as a lattice template at a deposition temperature within about 350 to about 500 Degrees Celsius, the polycrystalline silicon having an intrinsic semiconductor characteristic, forming a second conductor over the polycrystalline silicon in physical and electric contact with the resistive polycrystalline silicon, and forming a second wiring structure over the second conductor.

Abstract: A method of programming a non-volatile memory device includes providing a resistive switching device, the resistive switching device being in a first state and characterized by at least a first resistance, applying a first voltage to the resistive switching device in the first state to cause the resistive switching device to change to a second state wherein the second state is characterized by at least a second resistance, wherein the second resistance is greater than the first resistance, and applying a second voltage to the resistive switching device in the second state to cause the resistive switching device to change to a third state, wherein the third state is characterized by at least a third resistance, wherein the second voltage has a magnitude higher than a magnitude of the second voltage, and wherein the third resistance is greater than the second resistance.

Abstract: A non-volatile field programmable gate array includes a logic component, a transistor device comprising a gate structure, a first impurity region, and a second impurity region, the first impurity region coupled to the reconfigurable logic component, and a resistive switching device comprising a bottom electrode coupled to the first impurity region, a top electrode spatially extending in a first direction, and a resistive switching element coupled to the top electrode and to the bottom electrode at an intersecting region between the bottom electrode and the top electrode, wherein the resistive switching device stores a resistance state from a plurality of resistance states that indicates a configuration code for the reconfigurable logic component.

Abstract: Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections of the signal input lines and signal output lines. The RRAM memory cell can include a voltage divider comprising multiple programmable resistive elements arranged electrically in series across a VCC and VSS of the FPGA. A common node of the voltage divider drives a gate of a pass gate transistor configured to activate or deactivate the intersection. The disclosed RRAM memory can provide high transistor density, high logic utilization, fast programming speed, radiation immunity, fast power up and significant benefits for FPGA technology.