Abstract: Individual elements of an integrated circuit such as storage elements, (for example, latch elements), can be selectively coupled to select lines and probe lines. During normal operation the latches are not connected to the select lines and behave as a normal latch. During a write/control test operation, the latch is connected to a select line and data placed on the select line is provided to an input of latch. Thereafter, the latch is placed into a latching state in response to the probe line and the clock signal, latching the data provided from the select line into latch. In order to read/observe data, the clock line and probe line are controlled to route data onto the associated select line. In one embodiment the probe line controls a transistor switch that connects the select line to the input of the latch. The probe line also controls a transmission gate which is placed in the latch to toggle the latch between a latching condition and a non-latching condition, in response to signals on the probe line.

Abstract: A storage element for testing delay paths in integrated circuits is described. The storage element may be used in integrated circuits having matrices of probe and sense lines. The storage element generates a logic transition on an input to a delay path, the logic transition being closely synchronized with a clock signal. The storage element comprises a data input and a data output coupled to the input to the delay path. A master latch receives data from the data input through a first switch, the first switch being controlled by the complement of the clock signal. A slave latch receives data from the master latch through a second switch, the second switch being controlled by the true of the clock signal. A first sense input loads a first logic state into the master latch through a third switch, the first sense input being coupled to one of the IC's sense lines. The third switch is controlled by one of the IC's probe lines.

Abstract: An integrated circuit structure which employs at least two metal levels overlying an array of circuit elements. Each metal level contains signal routing resources which can be used for supplying power and interconnecting circuit elements. The metal levels include a first metal level directly overlying the array of circuit elements, intermediate metal levels (if there are more than two metal levels), and a top metal level overlying all other metal levels. Power carrying tracks are disposed in the top metal level. Power antennae are disposed in the first metal level, but only where necessary to provide power to the circuit elements. The power antennae are for connecting the power carrying tracks to the circuit elements. Power bridges are disposed in intermediate metal levels between the first metal level and the top metal level. The power bridges are for connecting the power carrying tracks to the power antennae.

Abstract: During application of a sequence of design verification patterns at the primary input pins of a sequential circuit IC, a test vector is spliced between patterns to test for a fault condition. As design verification patterns are applied in sequence, the state of the sequential circuit changes. To test for a select fault condition, the sequential circuit needs to be in a desired state. While in such desired state, a test vector is applied and select internal circuit element responses are monitored. If the desired state occurs during a sequence of design verification patterns, then the test vector is applied between successive patterns before the IC clock has a transition. By applying the test signal, monitoring the response, then reapplying the design verification pattern before the clock changes, the IC subsequent state which would occur had the test vector been omitted still occurs.

Abstract: An IC has local test circuitry including a test point array, instruction register, data register, probe line drivers and control/sense line drivers/receivers. To test the IC, the instruction register is loaded initiating the test circuitry to address select test points to receive control signals and to address other select test points at which response signals are to be sensed. Control signals are produced from the data register contents. The data register contents are derived as a function of the prior contents of the data register and a bit pattern formed from response signals of select test points. According to one embodiment, the prior contents are exclusively or'ed with the bit pattern of response signals to derive the new data register contents. A continuous test is performed by using prior response signals exclusively OR'ed to data register contents so as to generate subsequent control signals. Predesigned test sequences enable fast continuous testing of the IC.

Abstract: An IC having a test grid structure including intersecting probe lines and control/sense lines is used to apply desired logic states directly to internal transmission paths of select storage elements. A switch is located at each intersection for conducting the desired logic state to the internal transmission path. To achieve overwriting and storage of the desired logic state, the conventional storage element is modified to include a transmission gate activated by an overwrite enable signal. The overwrite enable signal is defined by one or more probe lines. To overwrite the contents of a storage element, the storage element is selected by turning on the switch with a probe line coupled to such switch, while the included transmission gate is disabled by receiving the overwrite enable signal. The logic state of the control/sense line is conducted into the storage element to the included transmission gate where it overwrites the current contents and is stored.

Abstract: A desired signal level is set at select storage elements of an integrated circuit without relying on signals applied to the primary input pins of the integrated circuit. Instead, a signal is applied through a test matrix to the input, output or internal line of a select storage element. With the drive of the applied signal being greater than the drive of the signals occurring at the select storage element of the integrated circuit, the applied signal level magnitude is forced upon the storage element. Once the drive of the applied signal is reduced relative to the drive of the storage element signals so as to be less than or equal to the drive of the storage element signals, the output level of the select storage element remains at the desired level. According to one embodiment, the power supply of the test electronics which generates the applied signal is of greater magnitude than the integrated circuit power supply at power up during the state-setting operation to achieve the greater relative drive.

Abstract: A method for operating a multiple input linear feedback shift register (LFSR) as a conventional shift register so that input multiplexers can be eliminated on each parallel input when associated with a CrossCheck matrix. A linear feedback shift register coupled through sense lines of a CrossCheck test matrix is operated as a serial shift register by inputting serial data at the serial data input while maintaining parallel input lines at a zero logic level. Further, zero logic level serial data (null data) is input serially through the shift register prior to the enabling of the parallel input. The method significantly reduces the number of logic structures required to shift the data out serially.

Abstract: An apparatus for testing for faults in an integrated circuit is attached to sense lines which are coupled to output nodes of logic gates of a test structure within an integrated circuit, such as a "Cross-Check" test structure built into an integrate circuit apparatus. A related method provide precharging of the sense lines to a known signal level prior to using the sense lines to sense the signal level at a test point. The apparatus combined with sense amplifiers or comparators attached to the sense lines may adjust detection levels of the comparators synchronously to test for either an output "one" minimum level (VOH) or output "zero" maximum level (VOL) to test for other classes of faults. The apparatus attached to the sense lines may inject charge into an output node of a logic gate at preselected times in a test sequence to modify the signal level at that output node to test for faults.