Abstract: An input/output circuit for increasing immunity to voltage spikes from voltage supplies is provided. The circuit includes a first pair of transistors each having their drains connected to an output terminal and their sources connected to voltage supplies. A mechanism is connected to electrically separated voltage supplies to alternately turn on one of the first pair of transistors responsive to an input signal. A transistor is utilized to provide feedback to limit the rise in a ground voltage supply as occurs during ground bounce.
Type:
Grant
Filed:
June 6, 1995
Date of Patent:
July 29, 1997
Assignee:
Crosspoint Solutions
Inventors:
Christopher E. Phillips, Michael G. Ahrens, Joseph G. Nolan, III, Laurence H. Cooke
Abstract: An antifuse particularly suitable for submicron geometries is presented. The antifuse is formed between a silicon layer, which could be a doped region of the semiconductor substrate, an epitaxial layer or a polysilicon layer, and an upper metal interconnection layer. In contact holes in a silicon dioxide layer insulating the silicon and metal interconnection layers from each other, the antifuses have a thick refractory metal layer having a top surface approximately at the same level as the top surface of the insulating layer. Depending upon the process used to deposit the refractory metal layer, a thin adhesion layer may be located immediately below the refractory metal layer. Between the underlying silicon layer and upper interconnection layer, a thin semiconductor material layer of amorphous silicon may be located either below the refractory metal layer or above it.
Type:
Grant
Filed:
May 3, 1991
Date of Patent:
August 3, 1993
Assignee:
Crosspoint Solutions
Inventors:
Pankaj Dixit, Monta R. Holzworth, Richard Klein, William P. Ingram, III