Abstract: An HVAC system to be installed in a vehicle comprises a battery management controller. The battery management controller comprises at least one connection for electrically coupling a first power source with a first voltage; at least one connection for electrically coupling a second power source with a second voltage; and a first memory storage device configured to record data collected by the battery management controller. The battery management controller is configured to run a temperature control system and to supply power to the temperature control system from a combination of the first and second power sources with a combined voltage, and wherein the second power source is disconnected when the combined voltage drops below a predetermined amount.

Abstract: An installable HVAC system used for a vehicle is disclosed. The HVAC system includes a housing, a compressor, a motor operatively coupled to the compressor; a condenser in fluid communication with the compressor; and a power management controller configured to run the motor with power from a given power source. The compressor, the motor, the condenser, and the power management controller are located within the housing. The housing is configured to attach to an existing HVAC system of the vehicle.

Abstract: A variable speed air compressing system includes a compressor, a motor configured to actuate the compressor, and a rectifier configured to receive alternating current from a first power source and to provide rectified direct current having a first voltage. The system also includes an inverter configured to receive the rectified direct current and to receive direct current from a second power source having a second voltage. The inverter is configured to provide alternating current to the motor. The alternating current provided to the motor is based on the rectified direct current if the first voltage is greater than the second voltage and the alternating current is based on the direct current from the second power source if the second voltage is greater than the first voltage.

Abstract: A field programmable gate array integrated circuit which has numerous features for testing prior to programming the antifuses in the integrated circuit is provided. The circuits used to program the antifuses are also used for much of the preprogramming testing. The functionality of continuous series transistors and latch logic blocks may be tested together with the continuity of their programmable connections. Programmable input/output buffer circuits and clock circuits which set the desired clock network paths may be tested with signals on a serial scan path which passes through the input/output buffer circuits and clock circuits. Process characterization tests without the requirement of high-speed test equipment are also provided.

Abstract: An FPGA includes primary resources and redundant resources. To program an FPGA to perform a desired function, a pattern of programmable elements to be programmed that takes advantage of primary resources only is first prepared. This pattern is then modified responsive to previously obtained information about defects within the FPGA. The modified pattern takes advantage of redundant resources as direct or indirect substitutes for FPGA elements rendered unusable by defects. The FPGA is programmed in accordance with the modified pattern.

Abstract: The present invention provides a voltage regulator especially adaptable for use with a field-programmable gate array (FPGA). The voltage regulator of the present invention rapidly generates an operating voltage for the core or nucleus logic elements upon application of external power while preventing degradation of the fuses. The core or regulated voltage of a FPGA can be set to a level that provides maximum performance with minimum power consumption or, alternatively, permits propagation delays and switching rates to be adjusted so as to compensate for die to die variation. Since it is common for electrical parameters of FPGA manufactured in different wafer fabrication facilities to vary, the voltage regulator is configurable as a true voltage regulator or, alternatively, as a pseudo-voltage regulator. The voltage regulator comprises an operational transconductance amplifier with a single gain stage followed by an NMOS source follower.

Abstract: The present invention provides for an antifuse in an integrated circuit, which has a stacked antifuse structure on a first interconnection line. The stacked structure has a first programming layer of amorphous silicon on the first interconnection line, a very thin insulating layer of silicon dioxide on the first programming layer, and a second programming layer of amorphous silicon on the very thin oxide layer. A second interconnection line on the second programming layer completes the antifuse which has a low leakage current between the first and second interconnection lines.

Abstract: Various improvements in the fabrication of an antifuse having silicon-amorphous silicon-metal layer structure are presented. Included are improved deposition techniques for the amorphous silicon layer. The improvements include steps for the fabrication of such an antifuse without the use of platinum and the resulting antifuse and contact structures.

Abstract: An integrated circuit having system logic with programmable elements, decoding logic coupled to the programmable elements for addressing the programmable elements and a plurality of input/output buffer circuits for passing signals between the system logic and the exterior of the integrated circuit through input/output terminals is disclosed. Each input/output buffer circuit comprises an output driver stage having an output terminal connected to an input/output terminal; and a plurality of cells, each cell having a multiplexer, a flip-flop connected to an output terminal of the first multiplexer for storing a signal from the first multiplexer, a latch connected to an output terminal of the flip-flop for storing a signal from the flip-flop, and a second multiplexer connected to an output terminal of the latch.

Abstract: The present invention provides for a method of forming an antifuse in an integrated circuit having a first insulating layer on a semiconductor substrate.

Abstract: An input/output circuit for increasing immunity to voltage spikes from voltage supplies is provided. The circuit includes a first pair of transistors each having their drains connected to an output terminal and their sources connected to voltage supplies. A mechanism is connected to electrically separated voltage supplies to alternately turn on one of the first pair of transistors responsive to an input signal. A transistor is utilized to provide feedback to limit the rise in a ground voltage supply as occurs during ground bounce.

Abstract: An improved RAM-logic tile (RLT) for use in a field programmable gate array (FPGA) is presented. The RLTs are located at the intersection of global horizontal and vertical lines. Wiring segments run locally between RLTs and contain programmable antifuses for connecting segments within an RLT and to neighboring RLTs. The RLTs are implemented with transmission gates and can be efficiently configured into a memory structure and/or logic device.

Abstract: An antifuse structure in an integrated circuit including a first interconnection line, a second interconnection line formed over the first interconnection line, and a plurality of programming layers between the first and second interconnection lines. Each pair of programming layers has a metal layer therebetween which dissolves with the programming layers to form a conducting link during the programming of such antifuse structure. Such antifuse structure may also include a conductive plug between the programming layers and the second interconnection line.

Abstract: A field programmable gate array integrated circuit which has numerous features for testing prior to programming the antifuses in the integrated circuit is provided. The circuits used to program the antifuses are also used for much of the preprogramming testing. The functionality of continuous series transistors and latch logic blocks may be tested together with the continuity of their programmable connections. Programmable input/output buffer circuits and clock circuits which set the desired clock network paths may be tested with signals on a serial scan path which passes through the input/output buffer circuits and clock circuits. Process characterization tests without the requirement of high-speed test equipment are also provided.

Abstract: The present invention provides for an integrated circuit antifuse structure having a first metal interconnection line, a programing layer over the first interconnection line, an etch stop layer over the programming layer, a sacrificial buffer layer over the etch stop layer, an insulating layer over the buffer layer, and a second metal interconnection line over the insulating layer. An aperture extends through the insulating layer and the buffer layer. The buffer layer has etching characteristics which are different from those of the insulating layer and the etch stop layer. This permits the aperture through the insulating layer to be formed with substantially vertical sides and through the buffer layer to be formed with substantially sloped sides. The second interconnection line extends into the aperture to form an antifuse structure with a low capacitance and a consistent programming voltage.

Abstract: A method and resulting antifuse structure in an integrated circuit include a first metal interconnection layer on a first insulating layer over the substrate of the integrated circuit, a second insulating layer over the first metal interconnection layer. The second insulating layer has a via therein and a programming layer is located in the via. Such programming layer includes a first region on the first metal interconnection layer which is removed from sides of the second insulating layer in the via, and a second region on the sides of the second insulating layer via. The first region has substantially a first thickness, the second region has substantially a second thickness which is greater than the first thickness. Upon programming the antifuse structure, a conducting link forms in the first region of the programming layer.

Abstract: A bandgap generator including an MOS current mirror, first and second bipolar transistors and an MOS transistor pair operating in saturation. Cascode transistors interconnect the saturation transistor pair and the MOS transistor pair. A bias resistor interconnects the one of the cascode transistors and one transistor of the MOS current mirror.

Abstract: An integrated circuit having system logic with programmable elements, decoding logic coupled to the programmable elements for addressing the programmable elements and a plurality of input/output buffer circuits for passing signals between the system logic and the exterior of the integrated circuit through input/output terminals is disclosed. Each input/output buffer circuit comprises an output driver stage having an output terminal connected to an input/output terminal; and a plurality of cells, each cell having a multiplexer, a flip-flop connected to an output terminal of the first multiplexer for storing a signal from the first multiplexer, a latch connected to an output terminal of the flip-flop for storing a signal from the flip-flop, and a second multiplexer connected to an output terminal of the latch.

Abstract: Various improvements in the fabrication of an antifuse having silicon-amorphous silicon-metal layer structure are presented. Included are improved deposition techniques for the amorphous silicon layer. The improvements include steps for the fabrication of such an antifuse without the use of platinum and the resulting antifuse and contact structures.

Abstract: A method of forming an antifuse in an integrated circuit having an insulating layer on a semiconductor substrate is provided. The method comprises forming a first metal interconnection layer on the insulating layer; forming a first barrier metal layer on the first metal interconnection layer; forming an amorphous silicon layer on the first barrier metal layer; forming another barrier metal layer atop the amorphous silicon layer; and forming a second metal interconnection layer on the second barrier metal layer. In at least one of the barrier metal forming steps, the barrier metal is formed by sputtering a barrier metal target which includes a semiconductor dopant, such as dopant.