Abstract: An amplifier circuit having four variable impedance nodes is provided. The amplifier has split transconductance current paths. Each half of the amplifier has two such current paths and each current path has a node which may be either a high impedance or low impedance node. Connected between the two nodes is a transistor which is utilized in driving the nodes to their either high or low impedance state. The invention is particularly useful in a folded cascode amplifier used for driving loud speakers. However, the circuitry may also be used in other amplifiers or other applications. Further, the linearity of the amplifier's transfer curve may be improved to provide improved performance for high resistive loads. Thus, a class A-B amplifier is provided which can drive a wide range of resistive loads with varying linearity requirements. Moreover, the amplifier can be programmed to provide a high linearity region depending on the desired application.

Abstract: An electronic circuit having a circuit stage, such as a switched capacitor stage or a 1-bit digital-to-analog converter and switched capacitor filter, that is loaded with a load impedance employs current feedforward to substantially cancel effects of the load impedance. A circuit includes a circuit stage and a load impedance following and connected to the circuit stage. A current feedforward circuit is connected to the load impedance, substantially cancelling the load impedance to improve linearity of the digital-to-analog converter or switched capacitor filter.

Abstract: An output driver is provided for operating in a primary power supply environment to drive an output system that can have voltages associated therewith that are higher than the primary power supply level. The driver includes a pull-down N-channel (34) and a pull-up P-channel transistor (44). An output node (40) is driven by the transistor (34) and (44). An N-channel protection device (38) is disposed between node (40) and transistor (34) and an N-channel transistor (48) is disposed between node (40) and transistor (44). Transistor (38) has the gate thereof biased to the primary supply voltage level and the transistor (48) has the gate thereof biased to a voltage slightly above the primary supply voltage level.

Abstract: A variable sample rate approximation technique is used for coding and recreating musical signals in a wavetable synthesizer. Many sounds inherently include one large fast transfer of energy followed by vibrations that dampen over time so that the bandwidth requirement of a musical sound is reduced with passing time. Using the variable sample rate approximation technique, musical sounds are classified into two categories, sustaining sounds and percussive sounds. A sustaining instrument creates a noisy stimulus then sustains the sound created by the noisy stimulus. A percussive instrument is also a noisy source and generates a sound signal having high frequencies that decay rapidly while sustaining instruments sustain at all frequencies nearly equally. The sustaining and percussive instruments have substantially different waveform characteristics but present similar conditions with respect to memory reduction.

Abstract: The present invention relates to a signal driver circuit for driving a liquid crystal display panel. The signal driver circuit provides level shifting within the circuit to lower the power consumption of a liquid crystal display module while still providing a wide analog voltage range to the liquid crystal display elements. The decoding circuits utilize a strand of abutting decode input transistors which are connected in series. Further to reduce the physical size of the decoding circuits, multiple decode circuits may share circuitry that decodes the most significant bits of a data word. A cell layout is utilized such that the most significant bits data are bused into the cell through metal lines and the least significant bits are bused in polysilicon that also operates as the gate of the decode input transistors. Moreover, the decode cell input transistors may all be of the same conductivity type.

Abstract: The present invention relates to a signal driver circuit for driving a liquid crystal display panel. The signal driver circuit provides level shifting within the circuit to lower the power consumption of a liquid crystal display module while still providing a wide analog voltage range to the liquid crystal display elements. The decoding circuits utilize a strand of abutting decode input transistors which are connected in series. Further to reduce the physical size of the decoding circuits, multiple decode circuits may share circuitry that decodes the most significant bits of a data word. A cell layout is utilized such that the most significant bits data are bused into the cell through metal lines and the least significant bits are bused in polysilicon that also operates as the gate of the decode input transistors. Moreover, the decode cell input transistors may all be of the same conductivity type.

Abstract: The present invention relates to a signal driver circuit for driving a liquid crystal display panel. The signal driver circuit provides level shifting within the circuit to lower the power consumption of a liquid crystal display module while still providing a wide analog voltage range to the liquid crystal display elements. The decoding circuits utilize a strand of abutting decode input transistors which are connected in series. Further to reduce the physical size of the decoding circuits, multiple decode circuits may share circuitry that decodes the most significant bits of a data word. A cell layout is utilized such that the most significant bits data are bused into the cell through metal lines and the least significant bits are bused in polysilicon that also operates as the gate of the decode input transistors. Moreover, the decode cell input transistors may all be of the same conductivity type.

Abstract: A method for changing the frequency of a low-pass Finite Impulse Response (FIR) filter with a fixed frequency clock utilizes a decimation-by-coefficient technique. The decimation-by-coefficient method utilizes a single set of coefficients that are stored in a coefficient Read Only Memory (ROM) (64). Data is input to an elastic buffer (60) with multiplications performed by a multiplication circuit (62). To realize a low frequency filter, all coefficients are utilized in the multiplication operations with sequential multiplies. These are accumulated in register (70), this providing a high precision filter. To increase frequency by a factor of two--to decimate the coefficients by a factor of two, it is only necessary to utilize every other coefficient, such that only a single fixed clock (78) is required.

Abstract: A variable gain echo suppressor is provided that utilizes two variable attenuators (410) and (412) that are disposed in the receive and transmit paths, respectively, of a communication system. An echo suppressor (414) receives the input from the far end and transmits the output from the near end and controls the two attenuators to set a variable gain therein. The echo suppressor utilizes a normalized power level which is normalized with respect to the background noise at the respective end and then takes the ratio of this normalized power and the normalized power at the opposite end to define an associated power ratio. This power ratio value is utilized to determine the attenuation for the associated end. When the power ratio is high, this indicates that a stronger signal is being received from that end and a small amount of attenuation is associated in the transmit path from that end. When they aye equal, this will result in both systems having approximately the same attenuation, a mid-level attenuation.

Abstract: A double-talk detector for an echo canceller includes power estimators (60) and (62) which are utilized to measure the ERLE value in a calculator (64). This ERLE value is stored in a register (70) when it is the largest value generated. This register (70) is updated whenever a new and better ERLE occurs. A fraction of the value in register (70) is utilized as an input to a comparator (88), and then compared to the current ERLE value. If the current ERLE differs from the SERLE in register (70) an inhibit signal is generated for blocking the updates of an adaptive filter (40). The value stored in the register (70) is periodically decremented to reduce the value thereof. This decrement operation is performed in response to detection of an utterance from the far-end.

Abstract: A differential input stage for a data conversion device includes two sections, one section for operating during a high stress portion of a charge transfer operation and one portion for operating during the remainder of the charge transfer operation. The first portion is comprised of two differential transistors (84) and (86) having the sources and bodies thereof connected to a source coupled node and connected through a switch (94) to a current source (92). The drains of transistors (84) and (86) are connected through switches (110) and (112), respectively, to output terminals. During the second half of the charge transfer operation, differential transistors (78) and (88), having the sources and bodies thereof connected to a source coupled node and connected to the current source (92) through a switch (90), are rendered operable with the drains thereof connected through switches (96) and (104), respectively, to the output terminals. Only one of the differential pairs is operable at any one time.

Abstract: A low precision Finite Impulse Response filter (FIR) is provided for filtering in a digital interpolation operation. The interpolation operation is comprised of two steps, a sampling rate conversion operation for interspersing zeroes between samples in an input sequence and a filtering step of filtering out images that result from this operation. The filtering operation utilizes a FIR filter that utilizes a low precision set of filter coefficients that are selected to tune the frequency response such that the low end frequency response including the pass band, the transition band, and the portion of the stop band immediately after the transition band provides a response equivalent to that commensurate with substantially higher precision FIR filter coefficients. A second, low pass filter section is provided for filtering the high frequency image energy at the output of the FIR filter to provide an overall filter response commensurate to that utilizing substantially higher precision FIR coefficients.

Abstract: An amplifier circuit having four variable impedance nodes is provided. The amplifier has split transconductance current paths. Each half of the amplifier has two such current paths and each current path has a node which may be either a high impedance or low impedance node. Connected between the two nodes is a transistor which is utilized in driving the nodes to their either high or low impedance state. The invention is particularly useful in a folded cascode amplifier used for driving loud speakers. However, the circuitry may also be used in other amplifiers or other applications.

Abstract: Method and circuitry for decreasing the recovery time of an MOS differential voltage comparator after an input voltage overdrive. At the beginning of a comparison cycle a reverse voltage is momentarily applied between the gates and sources of the input pair of source-coupled MOS transistors of sufficient magnitude to form a charge accumulation layer in the channel region of each of the transistors. Operating the differential voltage comparator in such manner substantially decreases the time required for the transistors to recover from an imbalance in their electrical characteristics caused by the input voltage overdrive.

Abstract: A digital-to-analog converter includes a delta-sigma modulator (10) that receives a digital input and converts it to a one-bit digital output stream. A fourth order switched-capacitor filter (12) is operable to receive the one-bit digital stream and convert it to an analog value int he sampled data domain. This is input to a switched-capacitor/continuous time buffer (14) which is then filtered by an active low pass filter (18) to provide an analog output. The switched-capacitor filter (12) includes four stages of integration (24), (30), (34) and (38). A one-bit DAC (20) is provided for converting the one-bit digital stream to an analog value. The one-bit DAC (20) is integral with the first stage of integration and is summed by a summing junction (22) with the output of the forth stage of integration (38).

Abstract: A tri-level capacitor structure includes a first shielded metal layer (36) that is disposed between an upper metal layer (38) and a lower polysilicon layer (34). The shielded metal layer (36) is separated from the polysilicon layer (34) by an oxide layer (42), and the upper metal layer (38) is separated from the shielded layer (36) by an oxide layer (44). The upper metal layer (38) and the polysilicon layer (34) are connected together to a node (48) to form an Insensitive Node, whereas the shielded layer (36) is connected to a node (46) that is referred to as the Sensitive Node (S). The capacitor structure is operable to be connected in a switched-capacitor configuration in a lossy integrator, such that the Sensitive Node is connected to the virtual ground of a differential amplifier (50). The integrator utilizing this configuration would be comprised of at least one switched-capacitor (56) on the input that has the plates thereof connected between ground and either an input signal V.sub.

Abstract: A low precision Finite Impulse Response filter (FIR) is provided for filtering in a digital interpolation operation. The interpolation operation includes two steps, a sampling rate conversion operation for interspersing zeroes between samples in an input sequence and a filtering step of filtering out images that result from this operation. The filtering operation utilizes a FIR filter that utilizes low precision filter coefficients that are selected to tune the frequency response such that the low end frequency response including the pass band, the transition band, and the portion of the stop band immediately after the transition band provides a response equivalent to that commensurate with substantially higher precision FIR filter coefficients, with the high frequency end of the stop band gradually increasing.

Abstract: A semiconductor capacitor for use in an analog-to-digital converter includes two parallel connected capacitors with separate lower plates (44) and (46) fabricated of polycrystalline silicon and upper plates (52) and (54) also fabricated of polysilicon. The plates are separated by capacitive oxide dielectric structures (48) and (50). They are interconnected such that the lower plate (44) of one capacitor is connected to the upper plate (54) of the other capacitor and the lower plate (46) of the other capacitor is connected to the upper plate (52) of the first capacitor. With such a configuration, the odd ordered non-linearities contributing to the voltage coefficient errors are cancelled.

Abstract: A low distortion output stage for a digital-to-analog converter that operates with a switched-capacitor filter is provided that drives a low output impedance load. A source follower transistor (266) drives an output node (260) and a load resistor (264). A first current source is provided by transistor (280) to provide a constant drain current to transistor (266). A transistor (282) provides a current source between the output node and low reference voltage. A first current source is provided by transistor (284) to source current to resistor (264) during positive output voltage swings and a current source provided by the transistor (286) sinks current from resistor (264) during low voltage swings. The current through transistor (284) is controlled to operate in class AB by a P-channel transistor (288) and a bi-polar transistor (290). Transistor (290) has the gate thereof connected to the drain of transistor (266), as does transistor (284).

Abstract: A delta-sigma modulator for a digital-to-analog converter includes a single adder (60) that has one input thereof multiplexed by multiplexer (62). Four shift registers (64), (66), (68) and (70) are connected in a serial fashion such that the data output by the adder (60) is input to the shift register (64) and the other input of adder (60) is connected to the output of register (70). In operation, the multiplexer (62) first selects the input data for input to the one input of adder (60) and selects the output of register (70) for the other input. This represents the first stage of integration wherein the accumulated value from a previous cycle is added to the present data. The output of the first stage of integration will be cycled through the registers for each overall cycle of the delta-sigma modulator. In the second stage of integration on the next clock cycle of the 4.times. clock, the multiplexer (62) selects the output of the register (68) for adding to the output of the register (70).