Abstract: A single chip audio system 100 includes a bus interface 101, digital to analog converters 110, an analog mixer 115, and analog spatial enhancement circuitry 7500. Digital to analog converters 110 convert digital audio data received through bus interface 101 into analog signals. Analog mixer 115 mixes signals received from digital to analog converters 110 with an analog signal received from an external source. Analog spatial enhancement circuitry 7500 enhances first and second mixed analog signals output from analog mixer 115.

Abstract: A data conversion device is provided for storing digital data in a DAT (332) at a 16-bit word length and then recovering the data at a 24-bit word length with an overall reduction in truncation noise that would be inherently associated with data at the 16-bit word length. This is facilitated by noise shaping the data at the 16-bit word length prior to storage in the DAT (332) with a noise-shaping filter (324). This results in truncation noise in the lower portion of the frequency band being shifted to the higher portion of the band. When the data is recovered, it is converted to a 24-bit word length and then processed through a bandpass filter to filter out the higher frequency noise to yield a signal that has a maximum noise equal to or less than that in the lower portion of the band stored in the DAT (332). Since the truncation noise was shifted from the lower band to the upper band, this is a lower noise level than that inherently associated with the 16-bit word length.

Abstract: A full-duplex communication device includes a transmit channel, a receive channel, and echo cancellers connected between the transmit channel and the receive channel. A plurality of control parameters and status indicators are defined for both channels. The plurality of control parameters are accessed via a writable interface for controlling operations of the communication device. Typically the control parameters are modified, enabled, and disabled based on an implemented control method and based on signal conditions, including noise, echo, tone, and other abnormal noise conditions. A writable access port enables a user to request tweaking, modification, enabling, and disabling of multiple features and controls. A readable/writable access port enables access to multiple status parameters that are indicative of the status of the communication device and channel operating conditions.

Abstract: A high resolution variable time delay circuit is disclosed. In one embodiment, a current digital to analog converter (DAC) is used to sequentially charge two capacitors having similar capacitance construction. A threshold level capacitor provides the threshold level to a comparator, and a ramping capacitor is used for ramping to the threshold to provide a delay time. The comparator provides a delayed pulse using the threshold level provided by the threshold level capacitor and the ramp provided by the ramping capacitor. Thus, resolution is better than that provided by digital elements alone. This circuit also automatically cancels errors due to capacitance variations and unit current variation of the DAC introduced during the manufacturing process. In another embodiment a single capacitor is used in combination with two current DACs and a comparator to provide a controllable time delay.

Abstract: A nonperiodic waveform is forced to a periodic character to facilitate looping of the waveform without introducing audible, and thus objectionable, sound artifacts. Nonperiodic waveforms are typically nonperiodic due to the presence of nonharmonic high frequency spectral components. In time, the high frequency components decay faster than low frequency components and looping of the waveform is facilitated. A loop forcing process and loop forcing filter facilitate looping of a nonperiodic waveform by accelerating the removal of the nonperiodic high frequency components. A loop forcing filter accelerates the removal of nonperiodic high frequency components using a comb filter having a frequency selectivity that varies in time.

Abstract: Early reflection and reverberation processing using a decimating filter simulates the high frequency attenuation of an actual physical and acoustical environment and advantageously reduces the memory storage and computational burden of the early reflection and reverberation processing method. A method of generating a reverberation effect in a sound signal includes decimating the sound signal in the sound signal path and forming an early reflection sound signal from the decimated sound signal. The early reflection sound signal has a reduced sample rate an attenuated high frequency components in comparison to the sound signal.

Abstract: An adaptive filter is provided which has fixed point or floating point data stored in a data RAM (74) and block scale floating point coefficients stored in a coefficient RAM (84). The data and coefficients are utilized in a filter algorithm which utilizes a multiplier and an accumulator to provide a convolution result. Coefficients are updated by adding the multiplied result of the data RAM value and the error value to the old value of the coefficient. This is done for all the coefficient values in the coefficient RAM. The error value indicates the difference between the filter output and the sampled near-end signal that is the echo. These new coefficients are examined and if any have a value above or all have a value below a predetermined threshold, then the mantissas of all the coefficients are shifted and the exponent adjusted in the next filter cycle.

Abstract: A dynamic volume control system in an audio processor uses gain and delay signals from a digital signal processor to dynamically control the user-selected volume of the audio processor. The digital signal processor executes audio signal processing operations that affect the gain applied to the audio signal so that the signal gain inherent in the signal processing path is known. The digital signal processor transfers the known gain and a predicted group delay signal to the dynamic volume control system to dynamically adjust the user-selected volume of the system. The digital signal processor is integrated with a digital-to-analog converter (DAC) in a dynamic volume control system that exploits the known gain and group delay to perform DAC volume control.

Abstract: A periodic multi-bit digital signal is synthesized having a frequency that is specified by the frequency of a periodic reference signal that is asynchronous with respect to a sampling clock of the periodic digital signal. In a digital video system, for example, a digital color subcarrier is synthesized and synchronized to a reference frequency of a crystal oscillator that is asynchronous with respect to a digital system clock for the digital video system. The periodic digital signal is generated by an adjustable digital oscillator clocked by the sampling clock. The frequency or phase of the periodic digital signal is compared to the frequency or phase of the periodic reference signal to produce an adjustment value for adjusting the periodic digital signal to synchronize the periodic digital signal with the periodic reference signal. The digital oscillator, for example, generates the periodic digital signal at the sampling rate by periodically incrementing an accumulator with the adjustment value.

Abstract: A method of generating zero detect flag at the output of an adder adding a first vector and a second vector to generate a third vector. A fourth vector is generated from the third vector a carry propagation vector and a carry generation vector. A fifth vector generated using an incremented third vector and an incremented carry propagation vector. A sixth vector generated from the fourth vector and the fifth vector. The bits of the sixth vector bitwise added to obtain the zero detection flag.

Abstract: A method of processing exponent data in an audio decoder. A first block of audio data is received including encoded exponent data. The encoded exponent data is packed into packed encoded words and stored in memory. Exponents are generated from the packed encoded words in memory for processing the first block of audio data. A second block of audio data is received. A determination is made as to whether a reuse flag has been set for the second block, and if the reuse flag has been set, exponents are generated from the packed encoded words memory for processing the second block of data.

Abstract: A reduced power FIR filter may be utilized as the digital decimation filter for a delta sigma ADC. The FIR filter utilizes a serial bit stream which is part of the control path of the filter. Thus, operations of the circuitry which comprises the filter may be controlled depending upon the data presented at the output of the delta sigma modulator. In particular, filter operations may be enabled only for a given digital state, for example, a digital 1 state. Thus, the filter operations may be enabled only for typically half of the bits from the serial bit stream and the power usage of the digital filter is significantly reduced.

Abstract: A sound or music synthesizer includes a reverberation simulator having a substantially reduced volatile storage, random access memory, or buffer size in comparison to conventional reverberation simulators by decimating the sound signal prior to applying the sound signal to a reverberator and then interpolating the sound signal generated by the reverberator to restore the sample frequency. The substantial reduction in buffer size enables the usage of the reverberator in low-cost, reduced size and single-chip environments.

Abstract: A novel serial port interface system and method are disclosed. The serial port interface system achieves a three-pin interface mode with only a serial data input pin, a serial data output pin, and a serial clock pin by allocating a bit in an on-chip register to identify a three-pin conversion-done mode. In this three-pin mode, the serial data output pin signals an external device that data is ready to be accessed. Also disclosed with this three-pin conversion-done mode is a single conversion data read and a continuous conversion data read that may be selected through two separate bits in an on-chip register. In another aspect, a multiple register access capability is disclosed that allows multiple on-chip registers to be accessed with a single read/write command. This is accomplished by allocating a register select address in a command register to identify a group of registers, such as all of the set-up registers (gain, offset and configuration).

Abstract: An amplifier circuit having four variable impedance nodes is provided. The amplifier has split transconductance current paths. Each half of the amplifier has two such current paths and each current path has a node which may be either a high impedance or low impedance node. Connected between the two nodes is a transistor which is utilized in driving the nodes to their either high or low impedance state. The invention is particularly useful in a folded cascode amplifier used for driving loud speakers. However, the circuitry may also be used in other amplifiers or other applications. Further, the linearity of the amplifier's transfer curve may be improved to provide improved performance for high resistive loads. Thus, a class A-B amplifier is provided which can drive a wide range of resistive loads with varying linearity requirements. Moreover, the amplifier can be programmed to provide a high linearity region depending on the desired application.

Abstract: A linear approximation to an exponential decay function exploits the characteristic of an exponential function that, at equal time intervals, the ratio of a parameter value at the beginning of the interval to the parameter value at the end of the interval remains constant. The technique for linear approximation of an exponential decay includes selection of a constant period or interval of time and selection of a constant ratio between the parameter value at the beginning of the constant period and the parameter value at the end of the constant period. In one embodiment, the selected ratio is one-half to exploit a binary arithmetic implementation. For a ratio of one-half, the exponential decay has a "half-life" in which only half the parameter value at the beginning of a period is left at the end of the selected "half-life time period".

Abstract: A calibrated digital-to-analog converter (DAC) is provided that includes a DAC having an interpolation circuit (40) and delta-sigma converter (44). The output of the delta-sigma converter (44) is input to a one-bit DAC (48) and the output thereof filtered by an analog low pass filter section (50). During a calibration procedure, a calibrated analog-to-digital converter (ADC) (22) is utilized that is operable to receive the analog output of the DAC with a "0" value input thereto through a multiplexer (58). The output of the ADC (22) represents the inherent error in the delta-sigma converter (44) and the analog filter section (50). This is stored in a register (62). In a second step of the operation, the contents of the register (62) are input through the interpolation circuit for interpolation thereof and storage in an offset register/latch circuit (56).

Abstract: A multiplier using a modified Booth algorithm dissipates power proportional to the magnitude of one of the operands, and logic races are eliminated using iterative networks.

Abstract: A high pass filter is provided utilizing a digital filter with coefficients that can be switched to provide for two responses, a fast response and a slow response. A first response is provided by an accumulator block (38) disposed between the output and a summing junction (30) on the input of the digital filter. A multiplexer (40) selects between this accumulator block (38) and a slow response accumulator block (42). The switching is effected with a zero crossing detect circuit (26). When the first and faster response brings the DC level down to a value that is close to zero, the second and slower response is selected to basically lock it to zero.

Abstract: A linear phase FIR filter includes a multiplication/accumulator engine which is operable to receive the multi-level data stream and multiply it by predetermined filter coefficients. The coefficients are symmetrical to allow a pre-addition operation wherein the data is first stored in a buffer and then the data for symmetrical coefficients added before multiplication by the coefficient. This results in a reduction of multiplications by a factor of two, thus allowing the multiplication/accumulator engine to operate at one-half the clock rate of the oversampled multi-level data bit stream.