Abstract: A synchronous serial communication link between a controller and a peripheral is resynchronized by the sending of a series of bits at a first logic level by the controller. The series of bits is long enough to ensure that the peripheral will decode a command word in which all of the bits are at the first logic level. The peripheral, upon decoding such a command word, resets the synchronization circuitry within the peripheral. The controller then sends a single bit of the opposite logic state followed by serial data. The peripheral, upon receipt of this bit of the opposite logic state, releases the synchronization circuitry from its reset condition and begins to decode the serial data in synchronization with the controller.

Abstract: A triple cascoded mirror active load includes three transistors (20), (26) and (28) in a first leg and three transistors (22), (30) and (34) in an output leg connected to an output node (18). The first leg receives a current on an input node (14) on the drain of transistor (20). Transistor (20) has the gate thereof connected to the drain of transistor (26) with the gates of transistors (24) and (30) connected together and to a bias voltage. Transistor (20) is mirrored to transistor (22) by connecting the gates thereof together. Similarly, the gates of transistors (28) and (34) are connected together and also to the node (14). In this manner, the node (14) receives a low impedance on the input thereto, whereas the gate of transistor (22) sees a high impedance thereto and with only two transistors, transistors 26 and 28, disposed in a loop as a ratioed cascoded configuration.

Abstract: A method and apparatus for calibration of errors in the analog reference voltage input of an analog-to-digital converter. A monolithic reference voltage generator is provided to generate the analog reference which includes a bandgap voltage reference (50) that outputs an untrimmed voltage and a temperature voltage. The untrimmed voltage and temperature voltage are input to a delta-sigma A/D converter (52) which has the output thereof processed through a digital filter (54) to output data on a data bus (58) for storage in an EEPROM (60). The EEPROM (60) is operable in one mode to store temperature history data and, in another mode, to store temperature compensation data. In one mode, temperature compensation parameters are retrieved from the EEPROM (60) and utilized by a multiplier/accumulator circuit (74) to generate compensation factors which are output as a digital word to a DAC (76) for controlling a trim circuit (14).

Abstract: A calibration method and apparatus to calibrate for non-linearities in a multi-level delta-sigma modulator (12) includes a calibration multiplexer (10) on the input for selecting in a calibration mode a zero voltage for input to the delta-sigma modulator (12). The delta-sigma modulator (12) has three levels, +1, 0, -1, the +1 level input to a processor (32) and the -1 level input to a processor (34). The processor (34) has the output thereof input to an compensation circuit (14) that offsets the value generated by the -1 processor (34) by a coefficient .delta.. The output of the compensation circuit (14) is then input to the minus input of a summation junction (36), which also receives the output of the processor (32), the output of summation junction (36) providing the digital output. The processors (32) and (34) are realized with a separate accumulator that switches between an associated filter coefficient and ground, the filter coefficient stored in a ROM (35). The .delta.

Abstract: A unity gain buffer for a DAC is provided that is disposed on the output of a switched-capacitor filter and sampled data/continuous time buffer. The unity gain buffer provides low-distortion operation with a high input impedance. Differential input transistors (190) and (200) are provided having the source thereof connected to a common source node (202). A current source transistor (214) provides a current source between node (202) and ground. Each of the drains of transistors (190) and (200) have a constant current source provided thereto by transistors (222) and (230). Cascode devices (216) and (226) are disposed in the drains of transistors (190) and (200) to maintain a constant V.sub.DS during large input common-mode conditions. Any bias variations in transistor (214) are absorbed by feedback transistors (232) and (234), which provide a variable current source to node (202). These are controlled by the voltages on the drains of transistors (190) and (200).