Patents Assigned to CSELT - Centro Studi E Laboratori Telecommuniazioni S.p.A.
  • Dynamic programmable logic arrays with NOR-NOR structure implemented in C-MOS technology
    Patent number: 4769562
    Abstract: The blocking circuits which, during precharge, inhibit the data passage to the AND and OR planes of a dynamic programmable logic array with NOR-NOR structure, implemented in C-MOS technology, comprise a pair of transistors with complementary channel doping, the first of which controls the signal passage to the AND or the OR plane, respectively, and the second inhibits the gates of the respective plane during precharge.
    Type: Grant
    Filed: July 30, 1987
    Date of Patent: September 6, 1988
    Assignee: CSELT - Centro Studi E Laboratori Telecommuniazioni S.p.A.
    Inventor: Guido Ghisio