Patents Assigned to CSEM, Centre Suisse d'Electronique et Microtechnique SA
  • Patent number: 6943637
    Abstract: The voltage controlled oscillator circuit includes a resonant circuit, with two inductive elements (L1, L2) and a variable capacitive element (CV), which is connected to a high potential terminal (VEXT) of a voltage source, and a pair of cross-coupled NMOS transistors (N1, N2), which is connected between two oscillating signal (VA, VB) output terminals of the resonant circuit. Each NMOS transistor of the pair is connected in parallel to a diode mounted NMOS transistor (N3, N4) so as to form a current mirror. An identical current is supplied to each diode mounted transistor in an oscillating signal amplitude regulation loop. Two resistors (R1, R2) series connected between the gates of the transistors of the pair (N1, N2) allow extraction of the common mode voltage to be stored in a filtering capacitor (Cm) in order to bias a reference NMOS transistor (N5) connected to a reference resistor (R3).
    Type: Grant
    Filed: November 26, 2003
    Date of Patent: September 13, 2005
    Assignee: CSEM, Centre Suisse d'Electronique et Microtechnique SA
    Inventor: David Ruffieux
  • Publication number: 20040104782
    Abstract: The voltage controlled oscillator circuit includes a resonant circuit, with two inductive elements (L1, L2) and a variable capacitive element (CV), which is connected to a high potential terminal (VEXT) of a voltage source, and a pair of cross-coupled NMOS transistors (N1, N2), which is connected between two oscillating signal (VA, VB) output terminals of the resonant circuit. Each NMOS transistor of the pair is connected in parallel to a diode mounted NMOS transistor (N3, N4) so as to form a current mirror. An identical current is supplied to each diode mounted transistor in an oscillating signal amplitude regulation loop. Two resistors (R1, R2) series connected between the gates of the transistors of the pair (N1, N2) allow extraction of the common mode voltage to be stored in a filtering capacitor (Cm) in order to bias a reference NMOS transistor (N5) connected to a reference resistor (R3).
    Type: Application
    Filed: November 26, 2003
    Publication date: June 3, 2004
    Applicant: CSEM CENTRE SUISSE D'ELECTRONIQUE ET MICROTECHNIQUE SA
    Inventor: David Ruffieux