Abstract: A brown-out detection circuit having a time sequence control function comprises: a voltage divider (110), a reference voltage source (120), a comparator (130) and a time sequence control module (140); wherein one terminal of the voltage divider (110) is connected to an external power supply, the other terminal of the voltage divider (110) is connected to a positive input of the comparator (130), the reference voltage source (120) is connected to an inverted input of the comparator (130), the time sequence control module (140) is connected to an output of the comparator (130), an output of the time sequence control module (140) serves as an output of the brown-out detection circuit; when a duration of a power supply voltage lower than a reference voltage is not shorter than a preset time, the time sequence control module (140) controls the output of the brown-out detection circuit to be inverted from a high level to a low level.

Abstract: An MEMS-based method for manufacturing a sensor comprises the steps of: forming a shallow channel (120) and a support beam (140) on a front surface of a substrate (100); forming a first epitaxial layer (200) on the front surface of the substrate (100) to seal the shallow channel (120); forming a suspended mesh structure (160) below the first epitaxial layer (200); and forming a deep channel (180) at a position on a back surface of the substrate (100) corresponding to the shallow channel (120), so that the shallow channel (120) is in communication with the deep channel (180). In the Method of manufacturing a MEMS-based sensor, when a shallow channel is formed on a front surface, a support beam of a mass block is formed, so the etching of a channel is easier to control, the process is more precise, and the uniformity and the homogeneity of the formed support beam are better.

Abstract: A low dropout linear regulator circuit comprises a voltage reference source module (100), an error amplifier (200), a reference voltage determining module (300), a power transmission device (400) and a feedback module (500); wherein the voltage reference source module (100) provides a reference voltage for the error amplifier (200), the reference voltage determining module (300) controls an enablement of the error amplifier (200) according to whether the voltage reference source module (100) is completely started, the error amplifier (200) controls ON/OFF of the power transmission device (400) according to the reference voltage provided by the voltage reference source module (100) and a feedback voltage provided by the feedback module (500). A chip having the above low dropout linear regulator circuit and a electronic device having the above chip are provided.

Abstract: A photolithography method and system based on a high step slope are provided. The method includes: S1, manufacturing a sacrificial layer with a high step slope on a substrate; S2, adopting a spin-on PR coating process to cover the sacrificial layer with a photoresist layer to form a photolithographic layer; S3, forming a mask pattern and a compensation pattern on a mask; and S4, performing photolithography processes, by a photolithography machine, on the photolithographic layer. By forming a slope-top compensation pattern and a slope compensation pattern on a mask to perform photolithography on the substrate of a sacrificial layer, a relatively wide compensation pattern is set in a part of the top of the slope with a small thickness, thereby compensating the overexposure at the top of the slope, reducing the error in the photolithographic pattern, and improving the precision of photolithography of the high step slope.

Abstract: A method for manufacturing an MEMS torsional electrostatic actuator comprises: providing a substrate, wherein the substrate comprises a first silicon layer, a buried oxide layer and a second silicon layer that are laminated sequentially; patterning the first silicon layer and exposing the buried oxide layer to form a rectangular upper electrode plate separated from a peripheral region, wherein the upper electrode plate and the peripheral region are connected by only using a cantilever beam, and forming, on the peripheral region, a recessed portion exposing the buried oxide layer; patterning the second silicon layer and exposing the buried oxide layer to form a back cavity, wherein the back cavity is located in a region of the second silicon layer corresponding to the upper electrode plate, covers 40% to 60% of the area of the region corresponding to the upper electrode plate, and is close to one end of the cantilever beam; exposing the second silicon layer, and suspending the upper electrode plate and the can

Abstract: A lateral double diffused metal oxide semiconductor field-effect transistor includes semiconductor substrates, body regions positioned in the semiconductor substrates, drift regions positioned in the semiconductor substrates, source regions and a body leading-out region which are positioned in the body regions and spaced from the drift regions, a field region and drain regions which are positioned in the drift regions, and gates positioned on the surfaces of the semiconductor substrates to partially cover the body regions, the drift regions and the field region, wherein the field region is of a finger-like structure and comprises a plurality of strip field regions which extend from the source regions to the drain regions and are isolated by the active regions; and the strip field regions provided with strip gate extending regions extending from the gates.

Abstract: A method for manufacturing an injection-enhanced insulated-gate bipolar transistor, comprising the following steps: an n-type substrate (12) is provided; a p-type doped layer (14) is formed on the n-type substrate (12); a hard layer (20) is formed on the p-type doped layer (14); a groove (40) extending to the n-type substrate (12) is formed by etching on the p-type doped layer (14); an n-type doped layer (50) is formed on the sidewalls and bottom of the groove (40); the hard layer (20) is removed; p-type impurities of the p-type doped layer (14) and n-type impurities of the n-type doped layer (50) are driven in together, where the p-type impurities are diffused to form a p-type base region (60), and the n-type impurities are diffused to form an n-type buffer layer (70); a gated oxide dielectric layer (80) is formed on the surface of the groove (40); and, a polysilicon layer (90) is deposited in the groove having formed therein the gate oxide dielectric layer (80).

Abstract: A NOR flash memory and its manufacturing method are provided in the present disclosure, they are in the field of flash memory. In the manufacturing method, a mask dielectric layer is formed on a second polysilicon layer of a gate stack structure. In addition, part of the mask dielectric layer is etched patternedly to expose part of the second polysilicon layer which is close to a source. Furthermore, the exposed second polysilicon layer is self aligned to form a metal silicide layer. Thus in the NOR flash memory, an unetched mask dielectric layer is substantially located between a metal silicide layer and a drain contacting hole of the NOR flash memory. A drain current between the gate electrode and the drain electrode is small, the above manufacturing method is not complex, a process window is large, a side effect is small, which are advantageous to large scale production.

Abstract: A trench-type DMOS device includes a substrate as a public drain region, an active region and a voltage-dividing ring formed on the substrate, and a first dielectric layer formed on the substrate. Multiple trenches are located on the first dielectric layer, and the trenches extend from the surface of the first dielectric layer into the interior of the substrate. The trenches comprise at least one first trench distributed in the active region and a second trench outside the active region. A gate oxide layer is formed in the trench and polycrystalline silicon is filled to form a gate. The active region further comprises a source electrode region and a P-type heavily doped region under the source electrode region. A second dielectric layer covers the first dielectric layer and the multiple trenches. A metal layer covers the second dielectric layer to form a first electrode region and a second electrode region.

Abstract: A method of producing a Macro Read Only Memory (MROM) memory based on a One Time Programmable (OTP) memory is provided. The method includes: removing a floating gate of a second P-type Metal Oxide Semiconductor (PMOS) transistor of an OTP memory cell for storing data “0” in an OTP memory map, such that the OTP memory cell being transferred to a MROM memory cell for storing data “0”, and retaining an original structure of the OTP memory cell for storing data “1” in the OTP memory map, such that the original structure being used as a MROM memory cell for storing data “1”, thus forming a MROM memory map; and producing a MROM memory according to a MROM memory map. The OTP memory map is debugged to determine data which can be changed into the MROM memory map, and an OTP process can be transferred into a MROM process by adjusting only one mask during a producing process.

Abstract: A method for manufacturing a semiconductor device according to this specification solves the problem in the prior art that the silicon on the edge of an oxide layer in an LDMOS drift region is easily exposed and causes breakdown of an LDMOS device. The method includes: providing a semiconductor substrate comprising an LDMOS region and a CMOS region; forming a sacrificial oxide layer on the semiconductor substrate; removing the sacrificial oxide layer; forming a masking layer on the semiconductor substrate after the sacrificial oxidation treatment; using the masking layer as a mask to form an LDMOS drift region, and forming a drift region oxide layer above the drift region; and removing the masking layer. The method is applicable to a BCD process and the like.

Abstract: An electrostatic discharge (ESD) protection device is provided. A proper trigger voltage is determined by providing an ESD doped injection layer into a PNPN structure and adjusting the injection energy and dosage of the ESD doped injection layer; a proper holding voltage is obtained by adjusting the size of the ESD doped injection layer, thus preventing the latch-up. The self-isolation effect of the electrostatic discharge protection device is formed on the basis of an epitaxial wafer high voltage process or a silicon-on-insulator (SOI) wafer high voltage process, the ESD protective device of the present invention can prevent the device from being falsely triggered due to noise interference. Compared with other known ESD protection devices, the device has the same electrostatic protection ability, much smaller area, and much lower cost.

Abstract: A monitoring structure and a relevant monitoring method for the silicon wet etching depth are provided. The structure includes a wet etched groove formed on a monocrystalline silicon material with at least two top surfaces thereof being rectangular; and the top surface widths of the grooves are Wu and W1 respectively, Wu=du/0.71, and W1=du/0.71, where du is the maximum wet etching depth to be monitored, and d1 is the minimum of the wet etching depth to be monitored. The method includes: performing anisotropic wet etching on a monocrystalline silicon wafer according to a pattern with a monitoring pattern, forming an etched groove to be monitored and a structure for monitoring the depth of the groove, and then monitoring the structure to monitor the wet etching depth. The etching depth of the groove can be monitored with low costs, and a higher monitoring accuracy is obtained.