Abstract: A system for providing content for output to a user device, the system comprising: an identification unit configured to identify a user device preference indicative of a reduction of an output property of the user device for one or more components of the content; a reduction unit configured to reduce a contribution, to the content, of the components to obtain reduced content; and a provision unit configured to provide the reduced content to the user device for output.

Abstract: A memory device includes a memory cell array; and a processing in memory (PIM) unit including a plurality of multiplication and accumulation (MAC) operators which is configured to perform multiply-accumulation operations based on data stored in the memory cell array. The plurality of MAC operators performs the multiply-accumulation operations based on the data in a first stage, and to perform partial sum operations based on result values of the multiply-accumulation operations in a second stage.

Abstract: An integrated development environment (IDE) for uses a generative artificial intelligence (AI) model to generate industrial control code in accordance with functional requirements provided to the industrial IDE system as natural language prompts. The system's generative AI model leverages both a code repository storing sample control code and a document repository that stores device or software manuals, program instruction manuals, functional specification documents, or other technical documents. These repositories are synchronized by digitizing selected portions of document text from the document repository into control code for storage in the code repository, as well as contextualizing control code from the code repository into text-based documentation for storage in the document repository.

Abstract: A data system and a data reading method are provided in the present disclosure. The data system includes a processor, a memory, and a storage device. The processor includes a file system in user space. The memory includes a memory buffer. The user file space system receives a reading request sent by an application end. The file system in user space reads prefetch data of a target file pre-stored in at least one buffer block of the memory buffer according to the reading request. In response to the file system in user space determining that a total reading amount of a last buffer block with stored data from the at least one buffer block being currently read exceeds a preset total amount, the file system in user space prefetches a next batch of prefetch data of the target file from the storage device and stores it in another buffer block. Therefore a data reading operation of high efficiency is achieved.

Abstract: An automotive electronic control unit includes an application configured to flatten a nested structure of a first configuration file in which keys-values are recorded in a nested structure. The application is also configured to substitute the flattened keys with symbols recorded in a schema table. The application is further configured to record the symbols in a second configuration file. The application is additionally configured to search for a key-value in the second configuration. The automotive electronic control unit also includes a memory configured to store the schema table and the second configuration file.

Abstract: According to one aspect of the present disclosure, a computer-executed method is provided. The method may include receiving a first request sent from a first virtual machine. The first virtual machine may be configured to emulate a host. The method may include establishing communication between the first virtual machine and a second virtual machine in response to the first request. The second virtual machine may be configured to emulate a memory system.

Abstract: A dimmer includes a TRIAC structured to conduct load current during an on phase and not conduct the load current during an off phase; a snubber circuit including a resistor and a capacitor electrically connected to the resistor at a node; and a bidirectional switch structured to transmit a gate current pulse to gate of the TRIAC to switch the TRIAC between the OFF phase and the ON phase, the bidirectional switch including a first MOSFET, a second MOSFET, a first resistor electrically connected to source of the first MOSFET and a second resistor electrically connected to source of the second MOSFET, drain of the first MOSFET being electrically connected to the node of the snubber circuit, and drain of the second MOSFET being electrically connected to the gate of the TRIAC.

Abstract: A wiring substrate includes a first build-up part including a first conductor layer, a first insulating layer, and first via conductors penetrating through the first insulating layer, a second build-up part including second conductor layers, second insulating layers, and second via conductors penetrating though the second insulating layers, a third build-up part including a third conductor layer, a third insulating layer, and third via conductors penetrating through the third insulating layers such that the second built-up part is formed between the first built-up part and the third build-up part. The first, second and third build-up parts are formed such that a diameter of each of the first via conductors is smaller than a diameter of each of the second via conductors and that the diameter of each of the second via conductors is smaller than a diameter of each of the third via conductors.

Abstract: A ROM cell includes first and second three-dimensional transistors. The second transistor is formed above the first transistor, and the channel portions of the first and second transistors overlap each other. First data is stored depending on whether first and second local interconnects connected to the nodes of the first transistor are connected to a same line, or different lines, out of a bit line and a ground power supply line. Second data is stored depending on whether third and fourth local interconnects connected to the nodes of the second transistor are connected to a same line, or different lines, out of a bit line and a ground power supply line.

Abstract: A semiconductor device has an active area and a terminal area surrounding the active area and includes a base region, a plurality of annular subregions, an insulating layer provided with a plurality of insulating layer openings, and a first conductive layer. The plurality of annular subregions includes a first annular subregion in contact with the base region. The first annular subregion includes a plurality of annular structures in contact with each other. All the annular structures contact the first conductive layer through the corresponding insulating layer openings. The base region, the annular subregions, and the annular structures have a second conductivity type.

Abstract: An HEMT device includes a semiconductor epitaxial layer, a source electrode, a drain electrode, a gate electrode, a field plate structure, a first passivation layer, and a second passivation layer. The gate electrode includes a gate foot and a gate cap. The field plate structure includes a first portion, a second portion, a third portion, an extension portion. The second passivation layer has a first groove. The first groove has a first sidewall and a second sidewall. The first sidewall forms a first inclining angle with an imaginary line parallel to a gate length direction. The second sidewall and the imaginary line form a second inclining angle. Both of the first inclining angle and the second inclining angle are formed outside the first groove, and the first inclining angle is greater than the second inclining angle. A method for manufacturing the HEMT device is also provided.

Abstract: A method for producing a semiconductor device includes forming a gate electrode, a source electrode, and a drain electrode on an upper surface of a semiconductor layer, forming a first insulating film on the gate electrode, and forming a field plate on the first insulating film, the field plate having a first metal layer and a second metal layer having a higher Mohs hardness than the first metal layer. The forming the field plate includes forming a resist mask having an opening, the opening exposing a portion of the first insulating film overlapping the gate electrode, forming the first metal layer and the second metal layer in this order on an upper surface of the resist mask and inside the opening, and removing the resist mask and a portion of the first and second metal layers that are disposed on the resist mask by a lift-off process.

Abstract: Techniques described herein include forming respective (different) types of metal silicide layers for p-type source/drain regions and n-type source/drain regions of nanostructure transistors of a semiconductor device in a selective manner that reduces process complexity. For example, a p-type metal silicide layer may be selectively formed over a p-type source/drain region (e.g., such that the p-type metal silicide layer is not formed over the n-type source/drain region) of a first nanostructure transistor, and an n-type metal silicide layer may be formed over the n-type source/drain region (which may be selective or non-selective) of a second nanostructure transistor. This provides a low Schottky barrier height between the p-type metal silicide layer and the p-type source/drain region, as well as a low Schottky barrier height between the n-type metal silicide layer and the n-type source/drain region. This reduces the contact resistance for both p-type source/drain regions and n-type source/drain regions.

Abstract: An array switch circuit system includes a substrate, a plurality of first conductive pads, a plurality of first row/column switches, a plurality of second conductive pads and a plurality of first transmission lines. The first conductive pads are spaced apart from each other on the substrate and arranged as an array. Each of the first conductive pads has a column/row position in the array. Each of the first column/row switches connects two adjacent ones of the first conductive pad corresponding to the same column/row position. The plurality of second conductive pads are disposed on a periphery of the first conductive pad. Each of the first transmission lines connects two of the second conductive pads, and includes a first conductor strip and two second conducting strips. The two second conducting strips are respectively located on both sides of the first conducting strip and are coplanar with the first conducting strip.

Abstract: According to one aspect of the disclosure, there is provided an integrated circuit die includes: a substrate including a front side and a back side opposite to the front side; a front structure including a first element layer on the front side of the substrate and a first wiring layer on the first element layer; and a back structure including a second element layer on the back side of the substrate and a second wiring layer on the second element layer.

Abstract: Implementations of semiconductor packages may include: a digital signal processor having a first side and a second side and an image sensor array, having a first side and a second side. The first side of the image sensor array may be coupled to the second side of the digital signal processor through a plurality of hybrid bond interconnect (HBI) bond pads and an edge seal. One or more openings may extend from the second side of the image sensor array into the second side of the digital signal processor to an etch stop layer in the second side of the digital signal processor. The one or more openings may form a second edge seal between the plurality of HBI bond pads and the edge of the digital signal processor.

Abstract: A solar cell is provided, including: a substrate; a passivation layer formed over a surface of the substrate; fingers penetrating the passivation layer to be electrically connected to the substrate and including first and second fingers alternatingly arranged; connection electrodes each in electrical contact with end portions of at least two adjacent first fingers on a same side and includes one of a sectional structure and a curved wave-like structure. The sectional structure includes at least a first connection section and a second connection section connected to each other, where the first connection section is connected to an end portion of a respective finger of the at least two adjacent first fingers, the first connection section and the respective finger has an included angle that is not equal to 180°, and the first connection section and the second connection section has an included angle that is not equal to 180°.

Abstract: A high-resolution display device is provided. The display device includes a plurality of light-emitting units emitting light of different colors. The light-emitting unit has a microcavity structure and intensifies light with a specific wavelength. In the light-emitting units emitting light of different colors, reflective layers with different thicknesses are formed, an insulating layer is formed to cover the reflective layers, and then a top surface of the insulating layer is subjected to planarization treatment, whereby an insulating layer with different thicknesses is formed. After that, light-emitting elements emitting white light are formed over the planarized top surface of the insulating layer to overlap with the respective reflective layers, whereby the light-emitting units that intensify different colors due to different optical path lengths are separately formed.

Abstract: A foldable display apparatus includes a display panel including a folding area and a non-folding area, the folding area configured to fold about a folding axis, a first lower retardation layer on the display panel, a second lower retardation layer between the display panel and the first lower retardation layer, a linear polarizer disposed on the first lower retardation layer, the linear polarizer having a polarization axis of 45±5° or 135±5° with respect to the folding axis of the display panel, and a window member on the linear polarizer.

Abstract: A display device according to an embodiment of the present invention includes: a base material including a display region having a plurality of pixels and a frame region; a lower electrode provided in each of the plurality of pixels; an organic material layer arranged on the lower electrode; an upper electrode arranged on the organic material layer and covering the display region; a conductor portion provided in the frame region and connected to the upper electrode; and a rib provided on the conductor portion, wherein the upper electrode is arranged on the conductor portion via the rib, a first contact portion where the upper electrode and the conductor portion contact each other is located in the frame region, the rib has a side surface located at an opposite side of the first contact portion from the display region, and an end portion of the upper electrode faces the side surface.