Abstract: A semiconductor device has a lower metal layer, a lower dielectric layer on top of the lower metal layer, an upper metal layer on top of the lower dielectric layer, an upper dielectric layer on top of the upper metal layer, and a contact region formed as a cavity that extends through the upper dielectric layer, the upper metal layer and the lower dielectric layer for access to a solder pad portion of the lower metal layer. A dielectric lining layer lines a peripheral cavity-confining surface of the cavity, and is transverse to a plane of the lower metal layer. The dielectric lining layer isolates the upper metal layer from the lower metal layer while permitting access to the solder pad portion of the lower metal layer. An electrical contact fills the cavity, and enables external electrical connection with the lower metal layer.

Abstract: A semiconductor device has a lower metal layer, a lower dielectric layer on top of the lower metal layer, an upper metal layer on top of the lower dielectric layer, an upper dielectric layer on top of the upper metal layer, and a contact region formed as a cavity that extends through the upper dielectric layer, the upper metal layer and the lower dielectric layer for access to a solder pad portion of the lower metal layer. A dielectric lining layer lines a peripheral cavity-confining surface of the cavity, and is transverse to a plane of the lower metal layer. The dielectric lining layer isolates the upper metal layer from the lower metal layer while permitting access to the solder pad portion of the lower metal layer. An electrical contact fills the cavity, and enables external electrical connection with the lower metal layer.

Abstract: A testing base for a semiconductor device includes a retaining seat, a base board and a press unit. The retaining seat has a top side formed with a receiving cavity. The receiving cavity is adapted to receive the semiconductor device therein. The base board is mounted in a bottom portion of the receiving cavity of the retaining seat. The base board has a contacting side that confronts a contact mounting side of the semiconductor device when the semiconductor device is received in the receiving cavity. The contacting side is provided with a plurality of conductive contact pads adapted to connect electrically and respectively with contact members on the contact mounting side of the semiconductor device. The base board further has a plurality of contact terminals that extend outwardly through the retaining seat and that are connected electrically to the contact pads.

Abstract: An integrated circuit packaging structure, which can accommodate two or four memory chips in a single package. The feature rests upon a packaging structure that makes independent data buses between two memory chips, while implementing in parallel the address buses and control buses, and finally encapsulates them within one package in the expectation of doubling the memory capacity without increasing the size of the package and the number of pins.