Abstract: The decoder is capable of locating a data signal within any horizontal line of a video signal, thereby eliminating the necessity for keeping track of the line numbers. The pre-data portion is detected and the data portion is stored in the same register. DC level restoration of the video signal is performed periodically during digitizing. When the decoder is used to receive a data signal in the standard FCC waveform, the clock run in portion, normally used for synchronization in conventional decoders, is detected and the operating rate of the register is adjusted to the rate of the data portion for a number of clock signals equal to the number of data bits to capture the data portion. Once the data has been captured, further signals are prevented from entering the register for approximately one frame to permit the stored data to be retrieved.

Abstract: A packet switching system includes encoding circuitry for generating and intermittently transmitting a plurality of data packets in serial bit stream format. Each data packet consists of a plurality of data words and one or more address words where each such word includes an initial constant value start bit, either a data byte or an address byte, and a steering bit which indicates whether the word is the last to occur address word in the packet. The address byte represents a dimensional identity common to all of the data words in the data packet. The system also includes decoding circuitry including a start bit decoder for sensing the presence of a start bit and a shift register having a number of storage locations equal to the total number of bits in the one or more address bytes, into which bits from the serial bit stream are serially shifted. A register control circuit enables the shift register to receive only the address or data byte bits.