Abstract: A digital-to-analog converter having series-connected transistors forming high impedance current sources for respective segmented resistor strings. A series transistor forming a current sink for one resistor string presents a high output impedance by utilizing a negative feedback amplifier. The effects of a headroom resistor and an offset resistor in one resistor string are negated by configuring an output amplifier with appropriate gain resistors. A highly accurate D/A conversion can be achieved by utilizing all resistors of the main and sub-resistor strings with the same value.

Abstract: A method is disclosed for forming resistor strings in a semiconductor material for a digital-to-analog converter having a main DAC resistor string and a sub-DAC resistor string. The main DAC resistor string is formed as two identical resistor strings connected in parallel and such that the bottom of one resistor string and the top of the other resistor string are connected to a first voltage. The other ends of the resistor strings are coupled to a second different voltage. A switch multiplexer serving two functions is connected between the resistor strings. Each switch of the multiplexer interconnects similar voltage nodes of each resistor string together to thereby average the voltage should the resistance values differ due to semiconductor process variations. The switch multiplexer also serves to select one resistor of each resistor string to couple the voltage thereacross to a sub-resistor string of the digital-to-analog converter.

Abstract: An embedded microprocessor two level security system in flash memory. The memory includes an address input and a memory space of addressable locations having a restricted area and a user area. Addressing one of a the addressable locations therein results in the output of information therefrom in response to the receipt of an associated address on the address input. A logic device is provided for determining if a received address on the address input corresponds to an attempt to access an addressable location in the restricted space for output of information therefrom as the result of execution of a program instruction from the user area by an external processor.

Abstract: A voltage monitor having a bandgap reference circuit driven by a voltage to be monitored. The bandgap reference circuit produces a voltage and a second voltage that each vary with the voltage to be monitored. The magnitudes of these voltages are compared by an open loop comparator to provide a high speed output state. The output of the voltage monitor can be used to monitor a supply voltage and produce a reset signal to a processor if the supply voltage falls to a magnitude below a specified threshold.

Abstract: An integrated circuit providing mixed signal processing. I/O pin interface circuits include logic gates and other circuits for processing digital and analog signals. Processor-controlled configuration circuits allow the various I/O pin interface circuits to process either analog or digital circuits. The I/O pins can be configured for digital or analog operation on the fly.

Abstract: A pin interface for an integrated circuit. The pin interface includes logic gates for processing digital signals, and analog lines for carrying analog signals. The pin interface includes circuits for disabling the digital circuits when configured to carry analog signals.

Abstract: An integrated circuit providing mixed signal processing. I/O pin interface circuits include logic gates and other circuits for processing digital and analog signals. Processor-controlled configuration circuits allow the various I/O pin interface circuits to process either analog or digital circuits. The I/O pins can be configured for digital or analog operation on the fly.

Abstract: An analog-to-digital converter configurable for converting both differential and single-ended analog signals. Charge sharing between two input capacitors and a DAC capacitor allow the full dynamic range of the ADC device to be used when full scale differential analog input signals are converted. When configured for single-ended operation, charge sharing of the half scale single-ended input analog voltage occurs between one input capacitor and the DAC capacitor to allow the full dynamic range of the ADC device to again be utilized.

Abstract: A parasitic insensitive capacitor in a D/A converter. A semiconductor substrate is provided having a first face upon which the semiconductor integrated circuit is formed with a first conductive layer disposed over a portion of the first face of the semiconductor substrate and separated therefrom by a first insulating layer to form the lower plate of the capacitor. A second conductive layer is disposed over a portion and less than all of the first conductive layer and separated therefrom by a second insulating layer to form the upper plate of the capacitor. A third conductive layer disposed above the first and second conductive layers and separated from the first conductive layer by a third insulating layer, the third conductive layer having an opening therein of substantially the same shape as the second conductive layer and wherein the peripheral edges of the opening are substantially aligned with the peripheral edges of the second conductive layer.

Abstract: In a segmented DAC having dual main DAC resistor strings and dual sub-DAC resistor strings, an interpolation circuit for averaging the selected voltage from each sub-DAC resistor string. A first switch multiplexer selects a voltage from the first sub-DAC resistor string, and a second switch multiplexer selects a similar voltage from a second sub-DAC resistor string. The selected analog voltages are coupled to high impedance inputs of a differential averaging circuit. An output voltage is fed back to the differential circuit. Once the differential averaging circuit settles, a quiescent feedback voltage exists which is exactly between the two analog voltages to be interpolated. The non-linearity of the DAC is substantially reduced.

Abstract: An digital-to-analog converter having main DAC resistor strings and sub-DAC resistor strings for converting MSB and LSB portions of a digital word into corresponding analog voltages. The main DAC resistor strings are driven by constant current sources to improve the linearity of the conversion process. The constant current sources present a high impedance to the main DAC resistor strings, thereby providing a more linear change in resistance during the conversion process, and reducing second-order harmonic nonlinearity.

Abstract: A digital-to-analog converter having a main DAC resistor string formed in a semiconductor material. The main DAC resistor string is formed as two identical resistor strings connected in parallel and such that the bottom of one resistor string and the top of the other resistor string are connected to a first voltage. The other ends of the resistor strings are coupled to a second different voltage. A switch multiplexer serving two functions is connected between the resistor strings. Each switch of the multiplexer interconnects similar voltage nodes of each resistor string together to thereby average the voltage should the resistance values differ due to semiconductor process variations. The switch multiplexer also serves to select one resistor of each resistor string to couple the voltage thereacross to a sub-resistor string of the digital-to-analog converter.

Abstract: A digital-to-analog converter (DAC) employs a main DAC resistor string and a sub-resistor string formed in a semiconductor material. A main DAC conversion circuit is formed with a headroom resistor in series with the main DAC resistor string. The headroom resistor provides an operating voltage for current drivers in the sub-resistor string. The headroom resistor is formed adjacent to the main DAC resistor string in the semiconductor material to provide street effect compensation thereto. In practice, the main DAC resistor string is formed as two sets of resistor strings. The headroom resistor is formed as a first resistor string adjacent one main DAC resistor string set, and as a second resistor string adjacent the other main DAC resistor string set. The plural resistors of the headroom resistor strings have resistor values equal to the plural resistors of the respective main DAC resistor string sets.

Abstract: A digital-to-analog converter having series-connected transistors forming high impedance current sources for respective segmented resistor strings. A series transistor forming a current sink for one resistor string presents a high output impedance by utilizing a negative feedback amplifier. The effects of a headroom resistor and an offset resistor in one resistor string are negated by configuring an output amplifier with appropriate gain resistors. A highly accurate D/A conversion can be achieved by utilizing all resistors of the main and sub-resistor strings with the same value.

Abstract: A programmable gain circuit for analog-to-digital converter. A switched capacitor network capacitively couples an analog reference from a DAC to a comparator so that the sampled amplitude of the input analog signal can be compared with said analog reference. The ratio of the capacitance of the sampling capacitor to that of the switched capacitor network establishes an effective gain to the analog signal being converted.

Abstract: A system on chip with ADC having serial test mode. An integrated circuit having a processing system with a system clock and a data conversion circuit is provided that is operable to convert data between the analog and the digital domain, the data converter utilizing the system clock during normal operation. A clock isolation circuit is provided for isolating the operation of the data converter from the system clock during a test mode. A serial clock is provided for generating a serial clock during the test mode independent of a system clock. Control circuitry is then operable for controlling the data converter during the test mode to convert data utilizing the serial clock at times not coinciding with the rising and falling edges of the system clock, such control circuit operating in response to receiving a test control signal.

Abstract: An analog-to-digital converter having a digital-to-analog converter section for converting a Z-bit digital word. The digital-to-analog converter section includes an MSB portion for receiving a predetermined portion of the upper most significant bits, M bits, of the digital word and providing a monotonic division, VINC, of a reference voltage to provide a first analog voltage. A SubDAC portion is provided for receiving the remaining portion of the digital word, N bits, and providing a monotonic division of the voltage VINC to provide a second analog voltage. A summing device sums the first analog voltage with the second analog voltage to provide an analog output voltage with an M+N bit resolution, Z=M+N.