Abstract: A hierarchical arrangement of security devices for securing a protected network through a plurality of security devices having security rules of descending strictness. The system includes a first security device between two networks, and a second security device coupled to the first security device. A frame is processed by the first security device if the first security device's security policy allows processing. If there is insufficient information for the first security device, the first security device passes the frame to the second security device for processing. Additional security devices may be added in a hierarchical chain as necessary or desired. Passing-off may also be prevented to provide multi-level security within a protected network.

Abstract: A method for demodulating a received spread-spectrum signal using a minimum-shift-keyed (MSK) receiver. Using the method, an in-phase-component signal and a quadrature-phase-component signal are generated from a received spread-spectrum signal. The in-phase-component signal and the quadrature-phase-component signal are then processed and combined in such a way as to estimate data of the received-spread-spectrum signal.

Abstract: A public key sterilization scheme for thwarting possible attacks based on choosing malicious public keys. A first user sends public key information to a certificate authority. The certificate authority manipulates the public key information, and sends certified version of the public key information to the first user. The first user verifies the certified key, and calculates a second private key.

Abstract: A method for demodulating a received spread-spectrum signal using a minimum-shift-keyed (MSK) receiver. Using the method, an in-phase-component signal and a quadrature-phase-component signal are generated from a received spread-spectrum signal. The in-phase-component signal and the quadrature-phase-component signal are then processed and combined in such a way as to estimate data of the received-spread-spectrum signal.

Abstract: A spread spectrum receiver correlator for a with filters matched to transmitter chip codes are implemented in digital circuits along with a digital circuit for acquisition and tracking of the arrival times of the chip codes. The digital circuit implementations are used for the noncoherent demodulation of pulse position spread spectrum modulation signals where the pulse is a carrier modulator by a chip code and for the noncoherent demodulation of multiple chip code modulation signals where each information symbol is represented by one of several chip codes modulating a carrier.

Abstract: A method for establishing and communicating synchronous, code division multiple access communications between a base station and a plurality of remote units. A plurality of remote-communications signals which have spread-spectrum modulation are transmitted from the plurality of remote units and arrive simultaneously at the base station. The method includes transmitting repetitively from the base station a access signal having spread-spectrum modulation and receiving the access signal at an accessing-remote unit. The accessing-remote unit transmits an echo signal which has spread-spectrum modulation. The echo signal is received at the base station and a time delay is measured between the access signal and the received echo signal. A protocol signal which has spread-spectrum modulation is transmitted to the accessing-remote unit, with the protocol signal communicating a chip codeword and the time delay measured at the base station.

Abstract: A processor chip for adding a first integer having a plurality of groups of bits to a second integer having a plurality of groups of bits modulo a fourth integer having n-bits. The first integer plus the second integer equals a third integer. The processor chip includes a first register for storing the first integer, a second register for storing the second integer, and feedback register for storing a feedback number. The feedback number is the two's complement of the fourth integer. A plurality of full adders is coupled to the first register and the second register, and adds each group of bits of the first integer to the corresponding group of bits of the second integer, to generate the third integer. The bits of each group are added asynchronously during a time period. Sequentially, a second group of bits of the first integer are added to the corresponding second group of bits of the second integer.

Abstract: A spread spectrum receiver with filters matched to transmitter chip codes are implemented in digital circuits along with a digital circuit for acquisition and tracking of the arrival times of the chip codes. The digital circuit implementations are used for the noncoherent demodulation of pulse position spread spectrum modulation signals where the pulse is a carrier modulator by a chip code and for the noncoherent demodulation of multiple chip code modulation signals where each information symbol is represented by one of several chip codes modulating a carrier.

Abstract: A method for handling off a transitioning-remote unit from a first microcell having a first base station communicating with a first plurality of remote units, to a second microcell having a second base station communicating with a second plurality of remote units. The first base station communicates to the first plurality of remote units using synchronous, code division multiple access at a first carrier frequency and a first power level. The second base station communicates simultaneously to the second plurality of remote units using synchronous, code division multiple access at a second carrier frequency and a second power level. The second power level is typically greater than the first power level. While the transitioning-remote unit transitions from first microcell to the second microcell, the second base station detects a power level of the remote-communications signal, exceeding a predetermined threshold, transmitted from the transitioning-mobile unit.

Abstract: A spread spectrum receiver with filters matched to transmitter chip codes are implemented in digital circuits along with a digital circuit for acquisition and tracking of the arrival times of the chip codes. The digital circuit implementations are used for the noncoherent demodulation of pulse position spread spectrum modulation signals where the pulse is a carrier modulator by a chip code and for the noncoherent demodulation of multiple chip code modulation signals where each information symbol is represented by one of several chip codes modulating a carrier.

Abstract: A integer encryptor and decryptor, with the integer encryptor comprising a pseudorandom source, a discrete-time source, guard-band means, and adding means. The pseudorandom source generates a random-data signal. The random-data signal is an integer that lies within a first-bounded range. The discrete-time source generates the input-data signal. The guard-band means is coupled to the discrete-time source. In response to the input-data signal, the guard-band means generates an output-data signal. For a second-limit number the guard-band means limits the output-data signal to lie within a second-bounded range. The second-limit number is less than the first-limit number. The modulo-adding means is coupled to the pseudorandom source and the guard-band means. The modulo-adding means repetitively adds the output-data signal with the random-data signal and a third-limit number and generates an encrypted-data signal.

Abstract: A bit density controller is capable of transmitting no more than 15 consecutive 0-bits to be sent serially in a data bit sequence, without a 1-bit, for operating on the AT&T T1 network. The bit density controller includes a state machine having a state index and a substitution device coupled to the state machine. The bit density controller additionally can include a buffer for storing at least one frame of the data bit sequence, a memory for storing overhead bits, and an overhead bit inserter for inserting overhead bits into the data bit sequence.

Abstract: The present invention provides for a processor chip for computing addition, multiplication, and exponentiation in a Galois Field of integers modulo a prime number p, GF(p). The invention includes twelve registers for storing n-bit integers, a full adder for shifting left and adding data stored in two of the registers. A feedback register is included for storing a n-bit number and means for generating a feedback number is provided, wherein the feedback number is generated from a prime number, p. Also included are modulo means for reducing data bits stored in the registers modulo a prime number p.

Abstract: A bit density controller is capable of transmitting no more than 15 consecutive 0-bits to be sent serially in a data bit sequence, without a 1-bit, for operating on the AT&T T1 network. The bit density controller includes a state machine having a state index and a substitution device coupled to the state machine. The bit density controller additionally can include a buffer for storing at least one frame of the data bit sequence, a memory for storing overhead bits, and an overhead bit inserter for inserting overhead bits into the data bit sequence.