Patents Assigned to Cypess Semiconductor Corporation
  • Patent number: 9431364
    Abstract: A multi-chip package is disclosed that has a construction capable of preventing and/or reducing electrical shorts caused by shifts in bond wires. The multi-chip package includes a die attach formed between connection points of a bond wire. The die attach is made of a non-conductive material and can be constructed so as to support or encompass a portion of the bond wire. By contacting the bond wire, the die attach restricts the motion of the bond wire by acting as a physical barrier to the bond wire's movement and/or as a source of friction. In this manner, undesired position shifts of the bond wires can be prevented, reducing device failures and allowing for improved manufacturing allowances.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: August 30, 2016
    Assignee: Cypess Semiconductor Corporation
    Inventors: Kiah Ling Tan, Sally Yin Lye Foong, Lee Changhak, Chin Nguk Lai
  • Patent number: 9142440
    Abstract: A method of producing a carrier structure for fabricating a stacked-type semiconductor device includes laminating thin plates for a lower carrier associated with an upper carrier. The method includes forming openings in the thin plates by etching or electric discharge machining. The lower carrier includes a magnet that is buried therein and the magnet maintains contact between the lower carrier and the upper carrier. A thin plate of the laminated thin plates is provided on each opposing surface of the magnet. The lower carrier further includes multiple magnets arranged around a periphery of the lower carrier and through a center region of the lower carrier that is between magnets on the periphery.
    Type: Grant
    Filed: December 3, 2008
    Date of Patent: September 22, 2015
    Assignee: Cypess Semiconductor Corporation
    Inventors: Masanori Onodera, Kouichi Meguro, Junichi Kasai, Yasuhiro Shinma, Koji Taya, Junji Tanaka