Abstract: A system for reconfiguring a peripheral device having a first configuration connected by a computer bus and a port to a host computer. The system comprises a first circuit and a second circuit. The first circuit may be configured to download information for a second configuration from the host computer into the peripheral device over the computer bus. The second circuit may be configured to electronically simulate, over the computer bus, a physical disconnection and reconnection of the peripheral device to reconfigure the peripheral device to the second configuration.

Abstract: A programmable skew buffer for optimizing the timing at the input or output pins of a memory device. The timing at each input and output pin of the memory device can be adjusted on an independent basis by coupling each input or output pin to a separate programmable skew buffer. The programmable skew buffer includes a clocked storage element that receives data from an input pin and outputs data to the memory array in the memory device when optimizing the input timing of the memory device, or receives data from the memory array in the memory device and outputs data to an output pin when optimizing the output timing of the memory device. The programmable skew buffer also includes a programmable delay circuit which generates one of a plurality of clock signals wherein each signal represents a delayed version of the system clock.

Abstract: A dynamic voltage reference circuit for generating one or more control signals for use in controlling a delay circuit or other circuit that requires compensation for process variations. The control signals are generated without drawing DC current at times other than when the active edge is propagating through the delay circuit. As a result, a reference generator with reduced power consumption is realized.

Abstract: A method of forming a multi-layer silicide gate structure for a MOS type semiconductor device that includes the processing steps of first providing a substrate, then depositing a gate oxide layer on the substrate, then depositing a first refractory metal silicide layer which has a first stoichometry on the gate oxide layer, and finally depositing a second refractory metal silicide layer which has a second stoichometry different than the first stoichometry on the first deposited refractory metal silicide layer.

Abstract: A programmable circuit for generating a clock signal is disclosed. The present invention provides a clock generator architecture that combines PLL-based clock generator circuitry with an on-chip EPROM in a monolithic clock generator chip. The clock generator allows for electrical configuration of various information including PLL parameters, input thresholds, output drive levels and output frequencies. The various parameters can be configured after the clock generator is fabricated. The parameters can be configured either during wafer sort or after packaging. The clock generator can be erased prior to packaging so programming can be verified.

Abstract: An improved high-speed sense amplifier is disclosed for use in programmable logic devices (PLDs) and complex PLDs. The sense amplifier includes a transresistance amplifier portion that provides a voltage potential to a first node of a memory array, which defines a read product term line. The current drawn by the memory array will cause the output of the amplifier to change states once a predetermined current level is reached, the predetermined trip point indicating that at least one memory cell is conducting. The amplifier includes an n-channel MOS transistor having its drain connected between a second node of the memory array, and its source to ground. The gate of the n-channel transistor is connected to the read product line. The n-channel limits current through the memory array by raising the potential at the second node, thus reducing the voltage drop across the memory array.

Abstract: A fast, fieldless flash memory cell includes an erase node having a control gate and a floating gate, both formed of polycrystalline silicon, a program transistor sharing the floating gate and control gate with the erase node, and a read transistor sharing the floating gate and control gate with the erase node and program transistor. The inventive memory cell is suitable for use in fast Programmable Logic Devices (PLDs) in the sub 5 nS range (2-5 nS), and other logic and memory parts.

Abstract: An output buffer with a variable output impedance is described. The buffer is designed so that the output impedance is set relatively low during the initial portion of the output transition in which the step would occur. The output impedance is increased near the end of the transmission to approximate the characteristic impedance of a transmission line driven by the buffer. Specifically, a first feedback circuit in the variable impedance output buffer outputs a first control signal in a first state during a first portion of the output transition. The first feedback circuit outputs the first control signal in a second state during a second portion of the output transition after the first portion. A first switched resistive element receives the first control signal from the first feedback circuit. The first switched resistive element increases the output impedance of the buffer in response to the first control single being in the second state.

Abstract: A power reduction circuit for selectively providing power to circuitry associated with and coupled to the power reduction circuit, which includes two transistors having current paths coupled in parallel and a nonvolatile programmable storage device having a current path coupled in series with the current paths of the two transistors. A control transistor which is also part of the power reduction circuit includes a current path between a power supply and the circuitry associated with and coupled to the power reduction circuit to selectively provide power to the associated circuitry. The control transistor has a control gate electrode which is coupled between the current path of the nonvolatile programmable storage device and the current paths of the two transistors. The state of the storage device controls the state of the control gate electrode of the control transistor and accordingly controls whether the power is supplied to the associated circuitry.

Abstract: A Bi-CMOS ECL semiconductor memory cell having a read word line, a write word line and a read bit line is disclosed. The cell includes a bistable circuit having complimentary outputs and also includes a first transfer device and a second transfer device, each having a gate electrode and a current path, the gate electrode of one transfer device being coupled to one of the complimentary outputs of the bistable circuit and the gate of the other transfer device being coupled to the other complimentary output, and the two current paths of the two transfer devices being coupled in series between the read word line and a first reference voltage. The cell further includes a bipolar transistor device having a base, a collector and an emitter.

Abstract: The invention relates to a random access memory having more than one port capable of accessing the same storage addresses. It provides a system for protection of data integrity at each port. First and second ports are capable of providing first and second address transition signals to enable data storage in a single memory address. A comparator is coupled to the first and second ports (1) for detecting address transitions indicating that the second port is addressing a particular memory address coincidentally when the first port also is addressing the same memory address, and (2) for generating a busy output signal for that address in the event of such coincidence. A transition detection circuit is used to detect the transition resulting from the removal of the busy output signal from the comparator and for providing a busy removal output signal equivalent to an address detection signal in the event of such detection.

Abstract: The invention pertains to an output buffer circuit capable of switching from the off state to the on state, and from the on state to the off state, without generating significant noise. The circuit includes an MOS inverter circuit having a first node adapted to be connected to one terminal of a power supply and a second node adapted to be connected to the other node, and having an input for receiving an input signal and an output for providing an output signal adapted to be connected to an output transistor. The circuit also has a first MOS transistor of one polarity type and one mode having its source-drain circuit coupled in series with the first node of the inverter circuit, and a second MOS transistor opposite in either polarity type or mode from the first MOS transistor, having its source-drain circuit coupled in series with the other node of the inverter circuit.