Abstract: Embodiments of the present invention relate to a switched-capacitor filter which comprises a first stage which itself comprises a first switched capacitor, a second stage which itself comprises a second switched capacitor, a switched capacitive element that couples the output of the first stage to the input of the second stage, and a non-switched capacitive element coupled from the output of the second stage to the input of the first stage to provide damping of the switched-capacitor filter. Both stages are implemented as inverting analog amplifiers and the filter is especially well suited to semiconductor manufacture. The switched capacitor filter is implemented as part of a user module in a programmable system on a chip, or PSoC.

Abstract: According to one embodiment, a method for storing content addressable memory (CAM) mask values may include storing mask values according to mask size in a mask register set (200). A mask register set (200) may include a number of locations arranged into regions (202, 204, 206 and 208). Each region (202, 204, 206 and 208) can store mask values of a different predetermined size.

Abstract: A method is described for forming a trench in a semiconductor substrate, which has a silicon layer, an oxide layer overlying the silicon layer, and a nitride layer overlying the oxide layer. The method includes etching the nitride layer to a nitride end point using a nitride etching chemistry, which includes a fluorinated hydrocarbon, oxygen, and an inert gas selected from the group consisting of neon, argon, krypton, xenon, and combinations thereof. Methods of making semiconductor devices, methods of reducing defects in semiconductor devices, and silicon wafers having trenches and isolation regions formed by the above-mentioned methods for forming a trench are also described.

Abstract: A method for applying instructions to a microprocessor during test mode is disclosed. In one embodiment of the present invention, first a test mode is entered, establishing the microprocessor as a slave and a test controller as a master. Then, the test controller fills an instruction queue with instructions to be executed. The instructions originate from a test interface. A memory, such as a program flash, coupled to the microprocessor is bypassed; thus, the microprocessor is forced to execute instructions from the instruction queue. In another embodiment, the test controller transfers to the instruction queue an instruction to be executed in the microprocessor. Then, the instruction causes instructions from a supervisory memory to be executed by the microprocessor. The supervisory memory comprises pre-determined test instructions.

Abstract: Prior to etching a poly-II layer during fabrication of an integrated circuit, a hydrofluoric acid (HF) dip is used to remove surface oxides from the poly-silicon layer and an anisotropic descumming operation is used to remove any resist material left over from a patterning operation. Following patterning, a long breakthrough etch (e.g., sufficient to remove 300-1500 ? of oxide) using an anisotropic breakthrough etchant (e.g., a fluorocarbon-based etchant) is performed before the poly-silicon layer is etched. The HF dip may be repeated if a predetermined time between the first dip and the etch is exceeded. The anisotropic descumming operation may be performed using an anisotropic anti-reflective coating (ARC) etch, e.g., a Cl2/O2, HBr/O2, CF4/O2 or another etch having an etch rate of approximately 3000 ?/min for approximately 10-20 seconds. The poly-silicon layer may be annealed following (but not prior to) the etch thereof.

Abstract: A method and a system for supplying power to a microcontroller with a single cell. One embodiment of the present invention discloses incorporation of a power supply pump circuit with the microcontroller and their dynamic interaction. The microcontroller sends its power requirements to the power supply pump circuit and in response, the power supply pump circuit controls the operating voltage with optimal efficiency. The dynamic update of power supply pump circuit results in an efficient use of the power supply pump circuit and thus results in a reduction of the number of dry cell batteries to only a single cell. Incorporation of the microcontroller and power supply pump circuit onto a single chip reduces the pin number requirements as well as the space required on the printed circuit board.

Abstract: A method of making a structure, includes filling a via hole with a conductive material, to form a via. The via hole passes through an etch-stop opening. In both directions along a first axis dielectric material is present between the via hole and edges of the etch-stop layer, and in both directions along a second axis, perpendicular to said first axis, dielectric material is not present between the via hole and edges of the etch-stop layer.

Abstract: Semiconductor process yield analysis in which the relationship between a wafer-level parameter and a die-level parameter is evaluated can be performed more quickly and with greater accuracy than has been the case with previous such yield analysis. The yield analysis can be performed by selecting regions of a semiconductor wafer or wafers from which parametric data is to be obtained for use in the analysis, based on one or more characteristics of the wafer(s). The yield analysis can be performed by grouping the parametric data based on both a grouping of the wafer-level parametric data and a grouping of the die-level parametric data. The yield analysis can be performed by grouping the parametric data in greater than 3 groups.

Abstract: In one embodiment, a buried-channel transistor is fabricated by masking a portion of an active region adjacent to a trench and implanting a dopant in an exposed portion of the active region to adjust a threshold voltage of the transistor. By masking a portion of the active region, the dopant is substantially prevented from getting in a region near an edge of the trench. Among other advantages, this results in reduced leakage current.

Abstract: A search engine system (100) is disclosed that can include at least one content addressable memory (CAM) device (102) arranged in a cascade configuration with at least one memory device (104), such as a static random access memory (SRAM). A CAM device (102) and memory device (104) may be connected to one another by point-to-point unidirectional connections. Command data issued by a device, such as a network processing unit (NPU) (110), can flow through all devices beginning with a CAM device (102) and eventually to a memory device (104). A memory device (104) can compare its own current result data with that of a previous device in a flow (such as another RAM device), and generate an output response.

Abstract: A system (100) may include a content addressable memory (CAM) device (102) and at least two requesting devices (104-0 and 104-n). Requesting devices (104-0 and 104-n) and a CAM device (102) may be connected by at least two communication links (106-0 and 106-n). A CAM device (102) may generate responses to requests, and assign a flow identification value for responses based on a communication link (106-0 and 106-n) on which a corresponding request was received.

Abstract: Embodiments of the present invention relate to an electronic device having programmable chip enable inputs in that each chip enable has a programmable assertion level, e.g., high or low. The device may be an integrated memory chip, e.g., SRAM device. On power up, a JTAG input port of the electronic device can be used to program a configuration register which contains bits for setting the assertion level of each chip enable input. The bits may be used to control respective multiplexers which select between a chip enable signal and its inverse. The chip enable signals may originate from a controller device. Regarding a memory device, the outputs of the multiplexers are coupled to chip enable signals of an integrated memory core.

Abstract: In one embodiment, a transistor is fabricated by forming a sacrificial emitter over a base, forming an oxide layer over the sacrificial emitter, removing a portion of the oxide layer, and then removing the sacrificial emitter. An emitter is later formed in the space formerly occupied by the sacrificial emitter. The sacrificial emitter allows a base implant step to be performed early in the process using a single masking step. The base may comprise epitaxial silicon-germanium or silicon.

Abstract: The present invention cascaded optical switching system includes architectures that provide three dimensional optical signal beam steering utilizing two dimension optical signal beam steering devices. A plurality of cascaded optical switches form a cascaded multi-dimensional optical switch fabric and direct an optical signal beam from one of the plurality of optical switches to another of the plurality of optical switches in a different dimension. In one embodiment, an incidence corrective device is included in a cascaded optical switch fabric and directs an optical signal beam in a shallow angle so that it strikes the next optical switch at a corrected incidence angle. A corrected incidence angle permits an optical signal beam to be forwarded at a relatively shallow angle to an optical switch located in a relatively close proximity on the optical switch fabric. The present invention also provides for refocusing of spreading optical signal beams and mitigation of signal loss.

Abstract: In one embodiment, a transistor comprises raised structures over a source region and a drain region. The raised source structures may comprise selectively deposited metal, such as selective tungsten. A self-aligned contact structure formed through a dielectric layer may provide an electrical connection between an overlying structure (e.g., an interconnect line) and the source or drain region. The transistor may further comprise a gate stack having a capping layer over a metal.

Abstract: A method of forming a photoresist includes forming a photoresist and patterning/developing it according to conventional methods. The photoresist is then subjected to ion implantation. The ions may be selected from the group consisting of argon, boron, boron fluoride, arsenic, phosphorous and nitrogen. The ion implantation during processing of the photoresist provides a stabilized photoresist and helps reduce CD loss, loss of the photoresist and formation of pin holes and striations.

Abstract: In accordance with one embodiment of the present invention, a circuit provides power stability functions for a microcontroller, during startup and normal operations performing power on reset functions and an array of power stability functions. The power on reset functions hold the microcontroller in a safe reset condition, reinforce the POR hold, and force its switch mode pump to drive up voltage provided to its common supply source. The power stability functions constitute a power on reset function, a power supply health, e.g., power state condition monitoring function, a control function for dynamically controlling the common supply source, and auxiliary functions, which may be protective of a flash memory. The power on reset function operates at a fixed and/or programmably changeable voltage levels. In one embodiment, the POR circuit is interconnected with a processor through a bus, enabling programmatic processor control of microcontroller power through interaction with the POR circuitry.

Abstract: One embodiment disclosed relates to a chemical-mechanical polishing process. The process includes performing chemical-mechanical polishing on an entire wafer lot without look ahead polishing of a first article wafer. A normalized polish rate is determined, and a process time for a next wafer lot is predicted using the normalized polish rate. Another embodiment of the invention relates to a polishing apparatus for chemical-mechanical planarization of semiconductor wafers.

Abstract: The invention enables construction of a microscope that has one or more advantageous characteristics as compared to previous microscopes. The microscope can be small and lightweight and, in particular, sufficiently small and light weight to be portable (e.g., smaller and far lighter than probe station microscopes used for microscopic liquid crystal analysis of a semiconductor device). The microscope can include a small and lightweight bellows that provides zoom capability. The microscope and/or a tripod that is used with the microscope can be implemented to provide objective lens position control capability (with any number of translational and/or rotational degrees of freedom). The microscope can include apparatus for ejecting a hot gas from the microscope to heat a specimen being observed with the microscope.

Abstract: A circuit that permits a processor in a microcontroller to adjust its clock speed on the fly. A processor receives a current clock signal and a phased current clock signal from a speed selection switch. A new speed selection switch provides a new clock signal and a phased new clock signal for comparison with the current clock signals. When the states of the current and new clocks appropriately align after issuance of a control from the processor, the new speed is switched into the current speed switch to permit the clock speed to change without producing spurious signals that cause unpredictable action in the processor. This advantageously allows the microcontroller to adjust its clock speed under program control.