Abstract: A system interface of a processing system receives an indication to initiate configuration of a programmable system. A processing device coupled to the system interface and associated with an integrated development environment, responsive to the indication, translates a hardware description code into one or more configuration files specific to the programmable system, the hardware description code to describe circuitry in the programmable system. The processing device further generates program code for a microcontroller of the programmable system based, at least in part, on the hardware description code, and configures the programmable system to implement the circuitry according to the configuration files and the program code. In addition, the processing device debugs the programmable system as configured by the configuration files and the program code.

Abstract: A device capable of operating at both a low power mode and at a high power mode which is connected to a host by a USB connection. The device includes a non-volatile memory which stores the operating state of the device when the host goes into hibernate mode and a flag which indicates that the host has entered the “hibernate” mode. When the device powers up, the previous state of the device is read from the memory. If the previous state was high power and the hibernate flag is set, the device restarts in high power mode without the need of any initialization to determine if the host will allow operation at high power speed mode. The device determines that the host is going into suspend mode (rather than power down mode) by determining if a suspend signal on the USB bus is followed by a power down operation.

Abstract: Methods and apparatus for remotely controlling an ATA device via a packet-based interface are disclosed. In one implementation, a remote host constructs command blocks corresponding to the ATA register-delivered commands that it would like executed. These command blocks are packetized and transported to a packet-to-ATA format bridge. At the bridge, each command block is parsed, and appropriate ATA read or write register commands are performed. The bridge performs requested data transfers via the packet-based interface. This embodiment can allow a non-ATAPI ATA device to connect externally to a host computer, e.g., via a USB plug-and-play packet interface. This can provide inexpensive and portable mass storage capability that does not require internal mounting or external routing of the short ATA cables that are intended for internal use only.

Abstract: A non-linear integrated phase locked loop circuit includes a phase detector for receiving a data signal and a clock pulse and for outputting a pump-up signal and a pump-down signal, a pulse divider connected to the phase detector for receiving the pump-up signal and the pump-down signal and producing a first output at predetermined multiples of the pump-up signal and a second output at predetermined multiples of the pump-down signal. A pulsed filter or integrator is connected to the pulse divider for receiving the first output and the second output and providing a frequency control signal for a voltage controlled oscillator. A three state amplifier is connected to the phase detector for receiving the pump-up signal and the pump-down signal and providing a phase control signal for a voltage controlled oscillator. The voltage controlled oscillator is connected to the pulsed filter and the amplifier for receiving the frequency control signal and the phase control signal and producing a corresponding output.

Abstract: A bi-directional control circuit for preventing the improper functioning of a pass transistor MN1 in a CMOS circuit due to abnormally high voltages on its source and drain nodes IO1 and IO2, involves controlling the voltage V1 on gate of MN1 using a gate node N1 that is coupled to supply voltage VCC under the control of two transistor pairs MN3, MN4 and MP3, MP4 that sense the voltages on IO1 and IO2, and an inverter pair MP2, MN2 having a voltage signal ENB input on its gates. If the voltages on nodes IO1 and IO2 both go high, MP3 and MP4 tend to turn OFF dropping gate voltage V1, via MP2, below VCC and tending to turn MN1 OFF. Leakage from node N1 in such event occurs through a small current bleed network formed by three transistors MN6, MN7, and MN8.

Abstract: A memory includes a memory array and a decoder. The memory array includes a plurality of memory locations and the decoder is coupled to receive an address for decoding the address to generate a select signal for selecting one of the plurality of memory locations in the memory array for a memory operation. The memory further includes circuitry coupled to the decoder for delaying the select signal for a first predetermined delay time to generate a delayed select signal and for selectively applying one of the select signal and the delayed select signal to the memory array. The circuitry applies the delayed select signal to the memory array during the memory operation before the select signal is to be deasserted such that address hold time of the memory operation is decreased without affecting the memory operation.