Patents Assigned to Cyress Semiconductor Corp.
  • Reducing tester channels for high pinout integrated circuits
    Patent number: 6971045
    Abstract: An integrated circuit generally comprising a plurality of input pads, an input circuit, and a core circuit. The input pads may be configured to receive a plurality of first input signals. The input circuit may be configured to generate a plurality of second input signals (i) equal to the first input signals while in an operational mode and (ii) responsive to a plurality of test vectors with timing generation determined by the first signals while in a test mode. The core circuit may be responsive to the second input signals.
    Type: Grant
    Filed: May 20, 2002
    Date of Patent: November 29, 2005
    Assignee: Cyress Semiconductor Corp.
    Inventors: Biswa M. Deb, Rajat Gupta