Abstract: An embodiment of the present invention is directed to a memory cell. The memory cell includes a first charge storage element and a second charge storage element, wherein the first and second charge storage elements include nitrides. The memory cell further includes an insulating layer formed between the first and second charge storage elements. The insulating layer provides insulation between the first and second charge storage elements.

Abstract: Apparatuses and methods of high-voltage capacitance-sensing circuits are described. One apparatus includes a capacitance-sensing circuit coupled to a capacitive-sense array of electrodes. The capacitance-sensing circuit includes a self-capacitance sensing channel, a first voltage source (e.g., a low-voltage drive source) to drive a reference voltage, and a second voltage source (e.g., high-voltage drive source) to drive a sensing voltage. The sensing voltage is greater in magnitude than the reference voltage. The capacitance-sensing circuit also includes 1) a first set of switches to selectively couple the self-capacitance sensing channel or the second voltage source to a sensing electrode of the capacitance-sensing array; and 2) a second set of switches to selectively couple the first voltage source or the second voltage source to a shielding electrode of the capacitance-sensing array.

Abstract: A device list is created including one or more device objects, wherein each device object represents a physical device coupled to a computer system, wherein each device object includes one or more device attributes of the physical device. The device list is indexed into using a device attribute.

Abstract: A microcontroller with a mixed analog/digital architecture including multiple digital programmable blocks and multiple analog programmable blocks in a communication array having a programmable interconnect structure. The single chip design is implemented by integration of programmable digital and analog circuit blocks that are able to communicate with each other. Robust analog and digital blocks that are flash memory programmable can be utilized to realize complex design applications that otherwise would require multiple chips and/or separate applications. The programmable chip architecture includes a novel array having programmable digital blocks that can communicate with programmable analog blocks using a programmable interconnect structure. The programmable analog array contains a complement of Continuous Time (CT) blocks and a complement of Switched Capacitor (SC) blocks that can communicate together.