Abstract: Provided is a routing method for determining a destination in a computer network having multiple interconnected nodes, the method for measuring packet delays among remotely located gateways and processing routing in application layers of the gateways using the packet delays. The routing method based on packet delay includes the steps of setting a re-routing interval and measuring one-way delays among gateways, exchanging the measured delays among the respective gateways and forming delay time tables, calculating an average one-way delay during the re-routing interval, and if a packet is received, applying the calculated average one-way delay to a predetermined algorithm and determining a path from a source gateway to a destination gateway, the path having the minimum delay. Therefore, an improved routing performance can be achieved in real time transmitting a packet by determining the minimum delay path to a destination by measuring packet delays among remotely located nodes in application layers thereof.

Abstract: A method for power saving routing in wireless networks is disclosed. The present invention calculates a distance to a destination node to select and estimate candidate nodes so as to reduce the amount of calculations in the event of routing. Furthermore, the invention repeats the algorithm by optimum value n so that accessibility to the destination node can be obtained. This enables more efficient routing.

Abstract: A small broadband monopole antenna including a shorted patch and a probe with a strip line that are electromagnetically coupled with each other. The probe with a strip line has a length of about ?/4, where ? is a wavelength. The strip line may be one of a spiral type, a folded type and a helix type. A resonance frequency of the antenna can be adjusted by varying the inductance and the capacitance of the resonance circuits. In addition, a double-band antenna or a single-band antenna having a broad bandwidth can be designed in accordance with application purpose of the antenna.

Abstract: A bit manipulation circuit which can speedily carry out unit operations, such as repetitive data shifts and modulo-2 additions, and bit extraction and insertion, so as to facilitate the operation of a communication system involved with such unit operations while maintaining simple hardware complexity. The bit manipulation circuit is suitable for use in a programmable processor comprising a register bank for temporarily storing an operand data and performs data encoding operation based data shift modulo-2 addition, and bit extraction and insertion operation. In the circuit, a shift addition array receives the operand data, generates a plurality of shifted data being shifted from the operand data by one bit through the bit width of the operand data, carries out Mod-2 additions in parallel with respect to the operand data and at least some of the plurality of shifted data, and stores the addition result in the register bank.

Abstract: The present invention relates to a method of detecting malicious scripts using a code insertion technique. The method of detecting malicious scripts according to the present invention comprises the step of checking values related to each sentence belonging to call sequences by using method call sequence detection based on rules including matching rules and relation rules, wherein the checking step comprises the steps of inserting a self-detection routine (malicious behavior detection routine) call sentence before and after a method call sentence of an original script, and detecting the malicious codes during execution of the script through a self-detection routine inserted into the original script. According to the present invention, since a detection routine is configured to operate during the execution of scripts, dynamically determined parameters and return values can be checked and thus detection accuracy can be improved.

Abstract: The present invention relates to a method for detecting malicious scripts using static analysis. The method of the present invention comprises the step of checking whether a series of methods constructing a malicious code pattern exist and whether parameters and return values associated between the methods match each other.

Abstract: The present invention relates to a method for detecting malicious code patterns in consideration of control and data flows. In the method of the present invention, a malicious code pattern is detected by determining whether values of tokens (variables or constants) included in two sentences to be examined will be identical to each other during execution of the sentences, and the determination on whether the values of the tokens will be identical to each other during the execution is made through classification into four cases: a case where both tokens in two sentences are constants, a case where one of tokens of two sentences is a constant and the other token is a variable, a case where both tokens of two sentences are variables and have the same name and range, and a case where both tokens of two sentences are variables but do not have the same name and range.

Abstract: An FFT (Fast Fourier Transform) processor is disclosed which is a core block of an OFDM (Orthogonal Frequency Division Multiplexing) or DMT (Discrete Multi-tone) MODEM. The FFT processor simultaneously performs sequential input and output by applying an in-place algorithm for a mixed-radix multi-bank memory, thereby realizing continuous processing with only a 2N-word memory having 4 banks. The FFT processor minimizes its complexity while satisfying a high-speed calculation requirement.